Introduction - If you have any usage issues, please Google them yourself
Even 1 state counter and output the function of the control circuit has two: one is to state the comparator output even 1 status to count, when the counter reaches the set value, is the number of meter counter output is 1, and control the "parallel input and state control circuit", "0" in the position of the parallel output. In this way, the input bits of the status comparison are "0", and the output is "0", indicating that the state has been synchronized; If the state is out of sync, the output of the "1" counter is always "0".
The other function of the "1" counter is that when the output is 1, the error count is counted. If the whole system has been synchronized, the state loses step, and the output state of the threshold detection circuit is controlled by the error statistics and the output state of the threshold detection circuit. The signal from the en end comes from the output of the state parallel comparator; CLR is the output signal from error statistics and threshold detection; CLK is the clock signal; Outp is the one count output. When a number reaches a set number, the output is 1; The parallel input and state controller is given to the output of 0 to achieve synchronization protection control.