FPGA and SOPC based on the use of VHDL language with asynchronous EDA-ching 0 and synchronous clock so that the adder counter

EXPT43_cnt10
............\cmp_state.ini
............\cnt10.asm.rpt
............\CNT10.CDF
............\cnt10.done
............\cnt10.fit.eqn
............\cnt10.flow.rpt
............\cnt10.map.rpt
............\cnt10.map.summary
............\CNT10.PIN
............\CNT10.QPF
............\CNT10.QSF
............\CNT10.QWS
............\CNT10.SOF
............\CNT10.VHD
............\CNT10.VWF
............\CNT10B.VHD
............\FLATSCH.SXR
............\SIM.CFG
............\STP1.STP
............\TRI2.VHD

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