This is a FPGA-BCD Encoder design. Compilers can be downloaded to the device simulation Altea.

example_proj
............\cmp_state.ini
............\db
............\..\altsyncram_njc1.tdf
............\..\example_proj.db_info
............\..\example_proj.project.hdb
............\..\example_proj.proj_top.sld_design_entry.sci
............\..\proj_top.asm.qmsg
............\..\proj_top.cmp.cdb
............\..\proj_top.cmp.ddb
............\..\proj_top.cmp.hdb
............\..\proj_top.cmp.rdb
............\..\proj_top.cmp.tdb
............\..\proj_top.csf.qmsg
............\..\proj_top.fit.qmsg
............\..\proj_top.hif
............\..\proj_top.map.cdb
............\..\proj_top.map.hdb
............\..\proj_top.map.qmsg
............\..\proj_top.pre_map.hdb
............\..\proj_top.rtlv.hdb
............\..\proj_top.rtlv_sg.cdb
............\..\proj_top.rtlv_sg_swap.cdb
............\..\proj_top.sgdiff.cdb
............\..\proj_top.sgdiff.hdb
............\..\proj_top.tan.qmsg
............\..\proj_top_cmp.qrpt
............\..\proj_top_hier_info
............\..\proj_top_syn_hier_info
............\example_proj.qpf
............\example_proj.qws
............\proj_top.qsf
............\proj_top.v
............\proj_top_bb.v
............\RAMs.mif

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