using VHDL description of 7 degrees LED digital display tubes, which were developed in FPGA

7段LED
......\db
......\..\DECL7S.asm.qmsg
......\..\DECL7S.cbx.xml
......\..\DECL7S.cmp.cdb
......\..\DECL7S.cmp.hdb
......\..\DECL7S.cmp.qrpt
......\..\DECL7S.cmp.rdb
......\..\DECL7S.cmp.tdb
......\..\DECL7S.cmp0.ddb
......\..\DECL7S.dbp
......\..\DECL7S.db_info
......\..\DECL7S.eco.cdb
......\..\DECL7S.fit.qmsg
......\..\DECL7S.hier_info
......\..\DECL7S.hif
......\..\DECL7S.map.cdb
......\..\DECL7S.map.hdb
......\..\DECL7S.map.qmsg
......\..\DECL7S.pre_map.cdb
......\..\DECL7S.pre_map.hdb
......\..\DECL7S.psp
......\..\DECL7S.rpp.qmsg
......\..\DECL7S.rtlv.hdb
......\..\DECL7S.rtlv_sg.cdb
......\..\DECL7S.rtlv_sg_swap.cdb
......\..\DECL7S.sgate.rvd
......\..\DECL7S.sgate_sm.rvd
......\..\DECL7S.sgdiff.cdb
......\..\DECL7S.sgdiff.hdb
......\..\DECL7S.signalprobe.cdb
......\..\DECL7S.sld_design_entry.sci
......\..\DECL7S.sld_design_entry_dsc.sci
......\..\DECL7S.syn_hier_info
......\..\DECL7S.tan.qmsg
......\DECL7S.asm.rpt
......\DECL7S.bsf
......\DECL7S.done
......\DECL7S.fit.eqn
......\DECL7S.fit.rpt
......\DECL7S.fit.summary
......\DECL7S.flow.rpt
......\DECL7S.map.eqn
......\DECL7S.map.rpt
......\DECL7S.map.summary
......\DECL7S.pin
......\DECL7S.pof
......\DECL7S.qpf
......\DECL7S.qsf
......\DECL7S.qws
......\DECL7S.sof
......\DECL7S.tan.rpt
......\DECL7S.tan.summary
......\DECL7S.vhd

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