In digital circuit design, usually there will be multiple clock domains, so it will involve cross-clock domain processing issues

Filename	Size	Update
跨时钟域的设计\CrossClockDomain.pdf	46055	2008-05-31
跨时钟域的设计\CrossClockDomain_design.pdf	113602	2008-03-11
跨时钟域的设计\Handshake protocols for de-synchronization.pdf	261645	2009-09-16
跨时钟域的设计\跨时钟域信号同步技术研究.pdf	4415258	2013-12-12
跨时钟域的设计\跨时钟域信号同步的IP解决方案.pdf	1315412	2013-12-12
跨时钟域的设计\跨时钟域信号同步的IP解决方案snps.pdf	1054054	2010-12-10
跨时钟域的设计\跨时钟域信号同步解决方案.pdf	1767179	2013-12-12
跨时钟域的设计\跨时钟域设计.pdf	629453	2011-12-29
跨时钟域的设计

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