class8_FSM Sequence detection machine is the most

Introduction - If you have any usage issues, please Google them yourself

Sequence detection machine is the most basic small experiment of Verilog state machine

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Filename	Size	Update
class8_FSM\img\状态分析.jpg	254971	2015-08-06
class8_FSM\prj\Hello.qpf	1274	2015-08-06
class8_FSM\prj\Hello.qsf	3902	2015-12-05
class8_FSM\prj\Hello.qws	1347	2015-12-05
class8_FSM\prj\output_files\Hello.done	26	2015-12-05
class8_FSM\prj\output_files\Hello.fit.smsg	703	2015-12-05
class8_FSM\prj\output_files\Hello.fit.summary	608	2015-12-05
class8_FSM\prj\output_files\Hello.jdi	224	2015-12-05
class8_FSM\prj\output_files\Hello.map.summary	462	2015-12-05
class8_FSM\prj\output_files\Hello.pin	33059	2015-12-05
class8_FSM\prj\output_files\Hello.sof	358644	2015-12-05
class8_FSM\prj\output_files\Hello.sta.summary	943	2015-12-05
class8_FSM\rtl\Hello.v	1017	2015-08-06
class8_FSM\testbench\Hello_tb.v	1490	2015-08-06
class8_FSM\文件夹模版.txt	216	2015-07-19
class8_FSM\prj\ip
class8_FSM\prj\output_files
class8_FSM\doc
class8_FSM\img
class8_FSM\prj
class8_FSM\rtl
class8_FSM\testbench
class8_FSM

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