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  • Update : 2017-11-20
  • Size : 132kb
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  • Author :苏克s****
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Four input NAND gate design
Packet file list
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FilenameSizeUpdate
test01\db\prev_cmp_test01.qmsg 5177 2017-11-12
test01\db\test01.(0).cnf.cdb 892 2017-11-12
test01\db\test01.(0).cnf.hdb 682 2017-11-12
test01\db\test01.cbx.xml 88 2017-11-12
test01\db\test01.cmp.hdb 10626 2017-11-12
test01\db\test01.cmp.rdb 5921 2017-11-12
test01\db\test01.cmp_merge.kpt 209 2017-11-12
test01\db\test01.db_info 139 2017-11-19
test01\db\test01.eda.qmsg 2707 2017-11-12
test01\db\test01.hier_info 93 2017-11-12
test01\db\test01.hif 376 2017-11-12
test01\db\test01.logic_util_heuristic.dat
test01\db\test01.lpc.html 372 2017-11-12
test01\db\test01.lpc.rdb 402 2017-11-12
test01\db\test01.lpc.txt 1060 2017-11-12
test01\db\test01.map.ammdb 128 2017-11-12
test01\db\test01.map.bpm 598 2017-11-12
test01\db\test01.map.cdb 2346 2017-11-12
test01\db\test01.map.hdb 10396 2017-11-12
test01\db\test01.map.kpt 209 2017-11-12
test01\db\test01.map.logdb 4 2017-11-12
test01\db\test01.map.qmsg 5177 2017-11-12
test01\db\test01.map.rdb 1377 2017-11-12
test01\db\test01.map_bb.cdb 1847 2017-11-12
test01\db\test01.map_bb.hdb 9581 2017-11-12
test01\db\test01.map_bb.logdb 4 2017-11-12
test01\db\test01.pre_map.hdb 10552 2017-11-12
test01\db\test01.pti_db_list.ddb 237 2017-11-12
test01\db\test01.root_partition.map.reg_db.cdb 218 2017-11-12
test01\db\test01.rtlv.hdb 10501 2017-11-12
test01\db\test01.rtlv_sg.cdb 912 2017-11-12
test01\db\test01.rtlv_sg_swap.cdb 203 2017-11-12
test01\db\test01.sld_design_entry.sci 269 2017-11-19
test01\db\test01.sld_design_entry_dsc.sci 269 2017-11-12
test01\db\test01.smart_action.txt 8 2017-11-12
test01\db\test01.tis_db_list.ddb 237 2017-11-12
test01\incremental_db\compiled_partitions\test01.db_info 139 2017-11-12
test01\incremental_db\compiled_partitions\test01.root_partition.map.cdb 2113 2017-11-12
test01\incremental_db\compiled_partitions\test01.root_partition.map.dpi 673 2017-11-12
test01\incremental_db\compiled_partitions\test01.root_partition.map.hbdb.cdb 1474 2017-11-12
test01\incremental_db\compiled_partitions\test01.root_partition.map.hbdb.hb_info 46 2017-11-12
test01\incremental_db\compiled_partitions\test01.root_partition.map.hbdb.hdb 10114 2017-11-12
test01\incremental_db\compiled_partitions\test01.root_partition.map.hbdb.sig 32 2017-11-12
test01\incremental_db\compiled_partitions\test01.root_partition.map.hdb 10387 2017-11-12
test01\incremental_db\compiled_partitions\test01.root_partition.map.kpt 212 2017-11-12
test01\incremental_db\README 653 2017-11-12
test01\output_files\test01.done 26 2017-11-12
test01\output_files\test01.eda.rpt 2712 2017-11-12
test01\output_files\test01.flow.rpt 8639 2017-11-12
test01\output_files\test01.map.rpt 22299 2017-11-12
test01\output_files\test01.map.summary 516 2017-11-12
test01\simulation\modelsim\modelsim.ini 11131 2017-11-12
test01\simulation\modelsim\msim_transcript 2625 2017-11-12
test01\simulation\modelsim\rtl_work\_info 1717 2017-11-12
test01\simulation\modelsim\rtl_work\_lib.qdb 49152 2017-11-12
test01\simulation\modelsim\rtl_work\_lib1_0.qdb 32768 2017-11-12
test01\simulation\modelsim\rtl_work\_lib1_0.qpg 8192 2017-11-12
test01\simulation\modelsim\rtl_work\_lib1_0.qtl 17005 2017-11-12
test01\simulation\modelsim\rtl_work\_vmake 29 2017-11-12
test01\simulation\modelsim\test01.vht 3764 2017-11-12
test01\simulation\modelsim\test01.vht.bak 3143 2017-11-12
test01\simulation\modelsim\test01_run_msim_rtl_vhdl.do 499 2017-11-12
test01\simulation\modelsim\test01_run_msim_rtl_vhdl.do.bak 499 2017-11-12
test01\simulation\modelsim\test01_run_msim_rtl_vhdl.do.bak1 499 2017-11-12
test01\simulation\modelsim\test01_run_msim_rtl_vhdl.do.bak10 499 2017-11-12
test01\simulation\modelsim\test01_run_msim_rtl_vhdl.do.bak11 499 2017-11-12
test01\simulation\modelsim\test01_run_msim_rtl_vhdl.do.bak2 499 2017-11-12
test01\simulation\modelsim\test01_run_msim_rtl_vhdl.do.bak3 499 2017-11-12
test01\simulation\modelsim\test01_run_msim_rtl_vhdl.do.bak4 499 2017-11-12
test01\simulation\modelsim\test01_run_msim_rtl_vhdl.do.bak5 499 2017-11-12
test01\simulation\modelsim\test01_run_msim_rtl_vhdl.do.bak6 499 2017-11-12
test01\simulation\modelsim\test01_run_msim_rtl_vhdl.do.bak7 499 2017-11-12
test01\simulation\modelsim\test01_run_msim_rtl_vhdl.do.bak8 499 2017-11-12
test01\simulation\modelsim\test01_run_msim_rtl_vhdl.do.bak9 499 2017-11-12
test01\simulation\modelsim\vsim.wlf 49152 2017-11-12
test01\test01.qpf 1348 2017-11-12
test01\test01.qsf 3601 2017-11-12
test01\test01.qws 1284 2017-11-19
test01\test01.vhd 291 2017-11-12
test01\test01.vhd.bak 281 2017-11-12
test01\test01_nativelink_simulation.rpt 997 2017-11-12
test01\simulation\modelsim\rtl_work
test01\incremental_db\compiled_partitions
test01\simulation\modelsim
test01\db
test01\incremental_db
test01\output_files
test01\simulation
test01
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