Using Verilog language to achieve a simple DDR SDRAM controller

DDR_MO\altclklock.v
DDR_MO\DDR.cr.mti
DDR_MO\DDR.mpf
DDR_MO\ddr_Command.v
DDR_MO\ddr_compile_all.v
DDR_MO\ddr_control_interface.v
DDR_MO\ddr_data_path.v
DDR_MO\ddr_sdram.v
DDR_MO\ddr_sdram_tb.v
DDR_MO\ddr_sdram_tb.v.bak
DDR_MO\modelsim.ini
DDR_MO\mt46v4m16.v
DDR_MO\Params.v
DDR_MO\pll1.v
DDR_MO\readme.txt
DDR_MO\vsim.wlf
DDR_MO\work\@_opt\_lib.qdb
DDR_MO\work\@_opt\_lib1_0.qdb
DDR_MO\work\@_opt\_lib1_0.qpg
DDR_MO\work\@_opt\_lib1_0.qtl
DDR_MO\work\@_opt\_lib2_0.qdb
DDR_MO\work\@_opt\_lib2_0.qpg
DDR_MO\work\@_opt\_lib2_0.qtl
DDR_MO\work\@_opt\_lib3_0.qdb
DDR_MO\work\@_opt\_lib3_0.qpg
DDR_MO\work\@_opt\_lib3_0.qtl
DDR_MO\work\@_opt\_lib4_0.qdb
DDR_MO\work\@_opt\_lib4_0.qpg
DDR_MO\work\@_opt\_lib4_0.qtl
DDR_MO\work\@_opt\_lib5_0.qdb
DDR_MO\work\@_opt\_lib5_0.qpg
DDR_MO\work\@_opt\_lib5_0.qtl
DDR_MO\work\_info
DDR_MO\work\_lib.qdb
DDR_MO\work\_lib1_6.qdb
DDR_MO\work\_lib1_6.qpg
DDR_MO\work\_lib1_6.qtl
DDR_MO\work\_vmake
DDR_MO\work\@_opt
DDR_MO\work\_temp
DDR_MO\work\_tempmsg
DDR_MO\work
DDR_MO

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