Introduction - If you have any usage issues, please Google them yourself
KF8F4122 is a lean instruction CPU for Harvard architecture. In this architecture, the program and data buses are independent of each other.
The length of the instruction byte is 16 bits, and most instructions can be executed within a machine cycle. A total of 73 instructions, efficiency
High, easy to extend instructions.
A variety of peripherals are included in the chip, including:
1 8 bit timers / counters T0
1 16 bit timers / counters T1
2 16 bit timers, T2/T3
1 12 bit, 14 channel ADC modules
2 way 8 bit PWM module
1 CCP (capture / compare /PWM5) modules
2 analog comparator modules
1 operational amplifier modules
1 UART (compatible LIN) modules
1 SSCI (I2C/SPI) modules
An optional voltage reference for the 2V/3V/4V
Hardware watchdog (with software enable)
Low voltage detection and low voltage reset module etc.
The chip is integrated with (1024+16) x 8 bit user data memory, RAM, 16K bytes of program memory, and 128 * 8
Bit DATA EEPROM.
KF8F4122