Read and write tests on the SDRAM press KEY0, will send test data, LED1 \ 2 will be constant, release KEY0, LED1 \ 2 flash, about 25 seconds later, LED1 constant, read and write success.

C5G_LPDDR2_RTL_Test\Avalon_bus_RW_Test.v
...................\c5_pin_model_dump.txt
...................\C5G_LPDDR2_RTL_Test.cdf
...................\C5G_LPDDR2_RTL_Test.done
...................\C5G_LPDDR2_RTL_Test.fit.smsg
...................\C5G_LPDDR2_RTL_Test.fit.summary
...................\C5G_LPDDR2_RTL_Test.jdi
...................\C5G_LPDDR2_RTL_Test.map.smsg
...................\C5G_LPDDR2_RTL_Test.map.summary
...................\C5G_LPDDR2_RTL_Test.pin
...................\C5G_LPDDR2_RTL_Test.pti_db_list.ddb
...................\C5G_LPDDR2_RTL_Test.qpf
...................\C5G_LPDDR2_RTL_Test.qsf
...................\C5G_LPDDR2_RTL_Test.qws
...................\C5G_LPDDR2_RTL_Test.sdc
...................\C5G_LPDDR2_RTL_Test.sof
...................\C5G_LPDDR2_RTL_Test.sta.summary
...................\C5G_LPDDR2_RTL_Test.tis_db_list.ddb
...................\C5G_LPDDR2_RTL_Test.v
...................\C5G_LPDDR2_RTL_Test_assignment_defaults.qdf
...................\demo_batch
...................\..........\C5G_LPDDR2_RTL_Test.bat
...................\..........\C5G_LPDDR2_RTL_Test.sof
...................\fpga_lpddr2.bsf
...................\fpga_lpddr2.cmp
...................\fpga_lpddr2.ppf
...................\fpga_lpddr2.qip
...................\fpga_lpddr2.sip
...................\fpga_lpddr2.spd
...................\fpga_lpddr2.v
...................\fpga_lpddr2
...................\...........\altdq_dqs2_acv_connect_to_hard_phy_cyclonev_lpddr2.sv
...................\...........\altera_avalon_mm_bridge.v
...................\...........\altera_avalon_sc_fifo.v
...................\...........\altera_avalon_st_pipeline_base.v
...................\...........\altera_mem_if_dll_cyclonev.sv
...................\...........\altera_mem_if_hard_memory_controller_top_cyclonev.sv
...................\...........\altera_mem_if_oct_cyclonev.sv
...................\...........\altera_mem_if_sequencer_cpu_cv_synth_cpu_inst.v
...................\...........\altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench.v
...................\...........\altera_mem_if_sequencer_mem_no_ifdef_params.sv
...................\...........\altera_mem_if_sequencer_rst.sv
...................\...........\altera_mem_if_simple_avalon_mm_bridge.sv
...................\...........\altera_merlin_arbitrator.sv
...................\...........\altera_merlin_burst_uncompressor.sv
...................\...........\altera_merlin_master_agent.sv
...................\...........\altera_merlin_master_translator.sv
...................\...........\altera_merlin_reorder_memory.sv
...................\...........\altera_merlin_slave_agent.sv
...................\...........\altera_merlin_slave_translator.sv
...................\...........\altera_merlin_traffic_limiter.sv
...................\...........\fpga_lpddr2_0002.v
...................\...........\fpga_lpddr2_p0.ppf
...................\...........\fpga_lpddr2_p0.sdc
...................\...........\fpga_lpddr2_p0.sv
...................\...........\fpga_lpddr2_p0_acv_hard_addr_cmd_pads.v
...................\...........\fpga_lpddr2_p0_acv_hard_io_pads.v
...................\...........\fpga_lpddr2_p0_acv_hard_memphy.v
...................\...........\fpga_lpddr2_p0_acv_ldc.v
...................\...........\fpga_lpddr2_p0_altdqdqs.v
...................\...........\fpga_lpddr2_p0_clock_pair_generator.v
...................\...........\fpga_lpddr2_p0_generic_ddio.v
...................\...........\fpga_lpddr2_p0_iss_probe.v
...................\...........\fpga_lpddr2_p0_parameters.tcl
...................\...........\fpga_lpddr2_p0_phy_csr.sv
...................\...........\fpga_lpddr2_p0_pin_assignments.tcl
...................\...........\fpga_lpddr2_p0_pin_map.tcl
...................\...........\fpga_lpddr2_p0_report_timing.tcl
...................\...........\fpga_lpddr2_p0_report_timing_core.tcl
...................\...........\fpga_lpddr2_p0_reset.v
...................\...........\fpga_lpddr2_p0_reset_sync.v
...................\...........\fpga_lpddr2_p0_timing.tcl
...................\...........\fpga_lpddr2_pll0.sv
...................\......

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