Using verilog language to achieve the transmission of chip AD9226

AD9226_acq\AD.bsf
..........\AD.v
..........\AD.v.bak
..........\AD1.v
..........\AD1.v.bak
..........\ADDA.asm.rpt
..........\ADDA.bdf
..........\ADDA.done
..........\ADDA.fit.rpt
..........\ADDA.fit.smsg
..........\ADDA.fit.summary
..........\ADDA.flow.rpt
..........\ADDA.jdi
..........\ADDA.map.rpt
..........\ADDA.map.summary
..........\ADDA.merge.rpt
..........\ADDA.pin
..........\ADDA.pof
..........\ADDA.qpf
..........\ADDA.qsf
..........\ADDA.restore.rpt
..........\ADDA.sof
..........\ADDA.sta.rpt
..........\ADDA.sta.summary
..........\ADDA.tcl
..........\ADDA_assignment_defaults.qdf
..........\cpu1.sdc
..........\cpu2.sdc
..........\DA.v
..........\db\ADDA.db_info
..........\..\ADDA.sld_design_entry.sci
..........\greybox_tmp\cbx_args.txt
..........\multiprocessors.sopc
..........\pll.bsf
..........\pll.ppf
..........\pll.qip
..........\pll.v
..........\pll_bb.v
..........\SIGN.bsf
..........\SIGN.inc
..........\SIGN.qip
..........\SIGN.v
..........\SIGN1.bsf
..........\SIGN1.qip
..........\SIGN1.v
..........\SIGN1_bb.v
..........\SIGN_bb.v
..........\SIN.qip
..........\SIN.v
..........\sopc_add_qip_file.tcl
..........\stp1.stp
..........\db
..........\greybox_tmp
..........\incremental_db
AD9226_acq

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