the testbench for ddr3

modelsim
........\data_gen.do
........\fifo.do
........\pll.do
........\system.do
sdram_test.cr.mti
sdram_test.mpf
src
...\data_gen
...\........\data_gen_module.v
...\........\data_gen_module_tb.v
...\........\datagene.v
...\........\datagene.v.bak
...\fifo
...\....\EasyCapture1.jpg
...\....\EasyCapture2.jpg
...\....\EasyCapture3.jpg
...\....\EasyCapture4.jpg
...\....\EasyCapture5.jpg
...\....\FIFO模块仿真说明.txt
...\....\fifo_test_module.v
...\....\fifo_test_module_tb.v
...\....\rdfifo.v
...\....\wrfifo.v
...\....\write_fifo_module.v
...\lib
...\...\220model.v
...\...\altera_mf.v
...\pll
...\...\clk_ctrl.v
...\...\pll_module.v
...\...\pll_module_tb.v
...\...\sys_ctrl.v
...\sdfifo
...\......\rdfifo.v
...\......\sdfifo_ctrl.v
...\......\wrfifo.v
...\sdram
...\.....\sdr_para.v
...\.....\sdram_cmd.v
...\.....\sdram_ctrl.v
...\.....\sdram_module.v
...\.....\sdram_module_tb.v
...\.....\sdram_top.v
...\.....\sdram_top.v.bak
...\.....\sdram_wr_data.v
...\system
...\......\system_module.v
...\......\system_module.v.bak
...\......\system_module_tb.v
...\......\system_module_tb.v.bak
vsim.wlf
wave
....\wave.do

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