tintileo en tarjeta Nexys2

tintileo\TopDesign.vhd
........\planAhead_run_3\planAhead.jou
........\...............\tintileo.data\sim_1\fileset.xml
........\...............\.............\constrs_1\fileset.xml
........\...............\.............\sources_1\fileset.xml
........\...............\.............\wt\project.wpc
........\...............\.............\..\webtalk_pa.xml
........\...............\planAhead.log
........\...............\tintileo.ppr
........\...............\planAhead_run.log
........\clock_divider_xst.xrpt
........\planAhead_run_1\planAhead.jou
........\...............\tintileo.data\sim_1\fileset.xml
........\...............\.............\constrs_1\fileset.xml
........\...............\.............\sources_1\fileset.xml
........\...............\.............\wt\project.wpc
........\...............\.............\..\webtalk_pa.xml
........\...............\planAhead.log
........\...............\tintileo.ppr
........\...............\planAhead_run.log
........\TopDesign.cmd_log
........\TopDesign.ucf
........\TopDesign_xst.xrpt
........\clock_divider.vhd
........\clock_divider_summary.html
........\tintileo.gise
........\TopDesign.lso
........\TopDesign_vhdl.prj
........\planAhead_pid4337.debug
........\TopDesign.xst
........\xst\work\hdpdeps.ref
........\...\....\sub00\vhpl01.vho
........\...\....\.....\vhpl00.vho
........\...\....\hdllib.ref
........\clock_divider.prj
........\pa.fromHdl.tcl
........\TopDesign_summary.html
........\tintileo.xise
........\TopDesign.syr
........\clock_divider.lso
........\clock_divider.syr
........\TopDesign.prj
........\planAhead_pid4032.debug
........\_xmsgs\pn_parser.xmsgs
........\......\xst.xmsgs
........\clock_divider.ngr
........\clock_divider.cmd_log
........\clock_divider.ucf
........\clock_divider.xst
........\clock_divider_envsettings.html
........\planAhead_run_2\planAhead.jou
........\...............\tintileo.data\sim_1\fileset.xml
........\...............\.............\constrs_1\fileset.xml
........\...............\.............\sources_1\fileset.xml
........\...............\.............\wt\project.wpc
........\...............\.............\..\webtalk_pa.xml
........\...............\planAhead.log
........\...............\tintileo.ppr
........\...............\planAhead_run.log
........\clock_divider.ngc
........\TopDesign_envsettings.html
........\planAhead_pid7212.debug
........\clock_divider.stx
........\webtalk_pn.xml
........\iseconfig\TopDesign.xreport
........\.........\tintileo.projectmgr
........\.........\clock_divider.xreport
........\xst\dump.xst\clock_divider.prj\ngx\notopt
........\...\........\.................\...\opt
........\...\........\.................\ngx
........\planAhead_run_3\tintileo.data\sim_1
........\...............\.............\constrs_1
........\...............\.............\sources_1
........\...............\.............\wt
........\..............1\tintileo.data\sim_1
........\...............\.............\constrs_1
........\...............\.............\sources_1
........\...............\.............\wt
........\xst\dump.xst\clock_divider.prj
........\...\work\sub00
........\planAhead_run_2\tintileo.data\sim_1
........\...............\.............\constrs_1
........\...............\.............\sources_1
........\...............\.............\wt
........\..............3\tintileo.data
........\..............1\tintileo.data
........\xst\dump.xst
........\...\work
........\...\projnav.tmp
........\...\file graph
........\planAhead_run_2\tintileo.data
........\planAhead_run_3
........\planAhead_run_1
........\ipcore_dir
........\xst
........\_xmsgs
........\planAhead_run_2
........\iseconfig
tintileo

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