I FPGA-based development code and I2C host computer code, can achieve I2C communication

I2C_Core\Controls
........\........\FPGA_Reference.ctl
........\........\Host_I2CBus_Options.ctl
........\........\I2C_Bus_State.ctl
........\........\i2c_Protocol_Timing.ctl
........\........\i2c_state.ctl
........\Documentation
........\.............\How to Get Started with this Code.pdf
........\.............\I2C Core for NI FPGA Modules_LV2010_(3).pdf
........\Example
........\.......\EEPROM_Example_HelloWorld.vi
........\.......\Example_TestStand2010_EEPROM-Testing.seq
........\FPGA Bitfiles
........\.............\I2CCore_FPGATarget_I2CCore[Top-Leve_A21C0FC1.lvbitx
........\FPGA
........\....\I2C_Core_[Top-Level].vi
........\....\SubVIs
........\....\......\I2C_IRQNotifyHost.vi
........\....\......\I2C_ReadBitFromSlave.vi
........\....\......\I2C_ReadByteFromSlave.vi
........\....\......\I2C_ReadReadMemoryBlock.vi
........\....\......\I2C_ReadSlaveACK.vi
........\....\......\I2C_Start.vi
........\....\......\I2C_Stop.vi
........\....\......\I2C_WriteBitToSlave.vi
........\....\......\I2C_WriteBytesToSlave.vi
........\....\......\I2C_WriteMasterACK.vi
........\....\......\I2C_WriteReadMemoryBlock.vi
........\....\......\I2C_WriteSlaveDeviceAddress.vi
........\....\......\I2C_WriteWriteMemoryBlock.vi
........\Host
........\....\I2C_Host_[Top-Level].vi
........\....\SubVIs
........\....\......\I2C_Host_Read.vi
........\....\......\I2C_HostHandleIRQ.vi
........\....\......\I2C_HostWriteCMD-ParamMemory.vi
........\I2C_Core.aliases
........\I2C_Core.lvlps
........\I2C_Core.lvproj

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