verilog source code of programable timer

UTIMER\Documents\UTimer_Core_DesignSpec_121007.doc
......\.........\UTimer_Core_Verification_Spec_200106_20.doc
......\.........\~$imer_Core_DesignSpec_121007.doc
......\gpt_Tests_Report.dat
......\rtl_verilog\gpt_core.v
......\...........\gpt_core.v.bak
......\...........\gpt_defines.v
......\...........\gpt_synchr.v
......\Utimer.cr.mti
......\Utimer.mpf
......\verification\scripts\gpt_core_rtl_run.do
......\............\.......\gpt_core_run.do
......\............\testbench\access_tasks.v
......\............\.........\gpt_core_tb.v
......\............\.........\reset_and_error_tasks.v
......\............\.........\Tests.v
......\............\.........\work\220model.v
......\............\.........\....\altera_mf.v
......\............\.........\....\cyclone_atoms.v
......\............\.........\....\GPT.cr.mti
......\............\.........\....\GPT.mpf
......\............\.........\....\gpt_core\verilog.asm
......\............\.........\....\........\_primary.dat
......\............\.........\....\........\_primary.vhd
......\............\.........\....\gpt_core_rtl_run.do
......\............\.........\....\gpt_core_rtl_run_cov.do
......\............\.........\....\.........tb\verilog.asm
......\............\.........\....\...........\_primary.dat
......\............\.........\....\...........\_primary.vhd
......\............\.........\....\....synchr\verilog.asm
......\............\.........\....\..........\_primary.dat
......\............\.........\....\..........\_primary.vhd
......\............\.........\....\vsim.wlf
......\............\.........\....\wave.do
......\............\.........\....\_info
......\............\.........\....\.opt\._work_gpt_core_fast.dt2
......\............\.........\....\....\._work_gpt_core_tb_fast.asm
......\............\.........\....\....\._work_gpt_core_tb_fast.dt2
......\............\.........\....\....\._work_gpt_synchr_fast.dt2
......\............\.........\....\....\._work__info
......\............\.........\....\....\_deps
......\vsim.wlf
......\work\_info
......\....\_lib.qdb
......\....\_lib1_0.qdb
......\....\_lib1_0.qpg
......\....\_lib1_0.qtl
......\....\_vmake
......\verification\testbench\work\gpt_core
......\............\.........\....\gpt_core_tb
......\............\.........\....\gpt_synchr
......\............\.........\....\_opt
......\............\.........\....\_temp
......\............\SRAM_Model_512x32\doc
......\............\testbench\work
......\............\scripts
......\............\SRAM_Model_512x32
......\............\testbench
......\Documents
......\rtl_verilog
......\verification
......\work
UTIMER

• We are an exchange download platform that only provides communication channels. The downloaded content comes from the internet. Except for download issues, please Google on your own.
• The downloaded content is provided for members to upload. If it unintentionally infringes on your copyright, please contact us.
• Please use Winrar for decompression tools
• If download fail, Try it againg or Feedback to us.
• If downloaded content did not match the introduction, Feedback to us，Confirm and will be refund.
• Before downloading, you can inquire through the uploaded person information

Nothing．