Write your own single cycle mips CPU and test engineering

scmips_cpu
..........\alu.v
..........\alu.v.bak
..........\alu_test.v
..........\alu_test.v.bak
..........\cpu.v
..........\cpu.v.bak
..........\cpu_top.v
..........\cpu_top.v.bak
..........\cu.v
..........\cu.v.bak
..........\define.v
..........\define.v.bak
..........\dff32.v
..........\dff32.v.bak
..........\mux2x32.v
..........\mux2x32.v.bak
..........\mux2x5.v
..........\mux2x5.v.bak
..........\mux4x32.v
..........\mux4x32.v.bak
..........\ram.v
..........\ram.v.bak
..........\regfile.v
..........\regfile.v.bak
..........\rom.v
..........\rom.v.bak
..........\scmips_cpu.cr.mti
..........\scmips_cpu.mpf
..........\vsim.wlf
..........\work
..........\....\alu
..........\....\...\verilog.prw
..........\....\...\verilog.psm
..........\....\...\_primary.dat
..........\....\...\_primary.dbs
..........\....\...\_primary.vhd
..........\....\alu_test
..........\....\........\verilog.prw
..........\....\........\verilog.psm
..........\....\........\_primary.dat
..........\....\........\_primary.dbs
..........\....\........\_primary.vhd
..........\....\cpu
..........\....\...\verilog.prw
..........\....\...\verilog.psm
..........\....\...\_primary.dat
..........\....\...\_primary.dbs
..........\....\...\_primary.vhd
..........\....\cpu_top
..........\....\.......\verilog.prw
..........\....\.......\verilog.psm
..........\....\.......\_primary.dat
..........\....\.......\_primary.dbs
..........\....\.......\_primary.vhd
..........\....\cu
..........\....\..\verilog.prw
..........\....\..\verilog.psm
..........\....\..\_primary.dat
..........\....\..\_primary.dbs
..........\....\..\_primary.vhd
..........\....\dff
..........\....\dff32
..........\....\.....\verilog.prw
..........\....\.....\verilog.psm
..........\....\.....\_primary.dat
..........\....\.....\_primary.dbs
..........\....\.....\_primary.vhd
..........\....\...\verilog.prw
..........\....\...\verilog.psm
..........\....\...\_primary.dat
..........\....\...\_primary.dbs
..........\....\...\_primary.vhd
..........\....\mux2x32
..........\....\.......\verilog.prw
..........\....\.......\verilog.psm
..........\....\.......\_primary.dat
..........\....\.......\_primary.dbs
..........\....\.......\_primary.vhd
..........\....\mux2x5
..........\....\......\verilog.prw
..........\....\......\verilog.psm
..........\....\......\_primary.dat
..........\....\......\_primary.dbs
..........\....\......\_primary.vhd
..........\....\mux4x32
..........\....\.......\verilog.prw
..........\....\.......\verilog.psm
..........\....\.......\_primary.dat
..........\....\.......\_primary.dbs
..........\....\.......\_primary.vhd
..........\....\ram
..........\....\...\verilog.prw
..........\....\...\verilog.psm
..........\....\...\_primary.dat
..........\....\...\_primary.dbs
..........\....\...\_primary.vhd
..........\....\regfile
..........\....\.......\verilog.prw
..........\....\.......\verilog.psm

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