USB2.0 IP core (detailed Verilog source code and documentation)

usb1_funct
..........\bench
..........\.....\CVS
..........\.....\...\Entries
..........\.....\...\Repository
..........\.....\...\Root
..........\.....\verilog
..........\.....\.......\CVS
..........\.....\.......\...\Entries
..........\.....\.......\...\Repository
..........\.....\.......\...\Root
..........\doc
..........\...\CVS
..........\...\...\Entries
..........\...\...\Repository
..........\...\...\Root
..........\...\README.txt
..........\...\STATUS.txt
..........\...\usb_doc.pdf
..........\rtl
..........\...\CVS
..........\...\...\Entries
..........\...\...\Repository
..........\...\...\Root
..........\...\verilog
..........\...\.......\CVS
..........\...\.......\...\Entries
..........\...\.......\...\Repository
..........\...\.......\...\Root
..........\...\.......\usbf_crc16.v
..........\...\.......\usbf_crc5.v
..........\...\.......\usbf_defines.v
..........\...\.......\usbf_ep_rf.v
..........\...\.......\usbf_ep_rf_dummy.v
..........\...\.......\usbf_idma.v
..........\...\.......\usbf_mem_arb.v
..........\...\.......\usbf_pa.v
..........\...\.......\usbf_pd.v
..........\...\.......\usbf_pe.v
..........\...\.......\usbf_pl.v
..........\...\.......\usbf_rf.v
..........\...\.......\usbf_top.v
..........\...\.......\usbf_utmi_if.v
..........\...\.......\usbf_utmi_ls.v
..........\...\.......\usbf_wb.v
..........\sim
..........\...\CVS
..........\...\...\Entries
..........\...\...\Repository
..........\...\...\Root
..........\...\rtl_sim
..........\...\.......\CVS
..........\...\.......\...\Entries
..........\...\.......\...\Repository
..........\...\.......\...\Root
..........\...\.......\bin
..........\...\.......\...\CVS
..........\...\.......\...\...\Entries
..........\...\.......\...\...\Repository
..........\...\.......\...\...\Root
..........\...\.......\run
..........\...\.......\...\CVS
..........\...\.......\...\...\Entries
..........\...\.......\...\...\Repository
..........\...\.......\...\...\Root
..........\syn
..........\...\CVS
..........\...\...\Entries
..........\...\...\Repository
..........\...\...\Root
..........\...\bin
..........\...\...\CVS
..........\...\...\...\Entries
..........\...\...\...\Repository
..........\...\...\...\Root
..........\...\...\comp.dc
..........\...\...\design_spec.dc
..........\...\...\lib_spec.dc
..........\...\...\read.dc
..........\...\log
..........\...\...\CVS
..........\...\...\...\Entries
..........\...\...\...\Repository
..........\...\...\...\Root
..........\...\out
..........\...\...\CVS
..........\...\...\...\Entries
..........\...\...\...\Repository
..........\...\...\...\Root
..........\...\run
..........\...\...\CVS
..........\...\...\...\Entries
..........\...\...\...\Repository
..........\...\...\...\Root

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