this code can easily be understood and teaches you how to divide the clock.

1、分频计数器\clkdivverilog\.sopc_builder\install.ptf
.............\.............\clkdiv.asm.rpt
.............\.............\clkdiv.cdf
.............\.............\clkdiv.done
.............\.............\clkdiv.dpf
.............\.............\clkdiv.fit.rpt
.............\.............\clkdiv.fit.smsg
.............\.............\clkdiv.fit.summary
.............\.............\clkdiv.flow.rpt
.............\.............\clkdiv.map.rpt
.............\.............\clkdiv.map.summary
.............\.............\clkdiv.pin
.............\.............\clkdiv.pof
.............\.............\clkdiv.qpf
.............\.............\clkdiv.qsf
.............\.............\clkdiv.qws
.............\.............\clkdiv.tan.rpt
.............\.............\clkdiv.tan.summary
.............\.............\clkdiv.v
.............\.............\clkdiv.v.bak
.............\.............\clkdiv_assignment_defaults.qdf
.............\.............\db\clkdiv.asm.qmsg
.............\.............\..\clkdiv.asm_labs.ddb
.............\.............\..\clkdiv.cbx.xml
.............\.............\..\clkdiv.cmp.cdb
.............\.............\..\clkdiv.cmp.hdb
.............\.............\..\clkdiv.cmp.kpt
.............\.............\..\clkdiv.cmp.logdb
.............\.............\..\clkdiv.cmp.rdb
.............\.............\..\clkdiv.cmp.tdb
.............\.............\..\clkdiv.cmp0.ddb
.............\.............\..\clkdiv.db_info
.............\.............\..\clkdiv.eco.cdb
.............\.............\..\clkdiv.fit.qmsg
.............\.............\..\clkdiv.hier_info
.............\.............\..\clkdiv.hif
.............\.............\..\clkdiv.map.cdb
.............\.............\..\clkdiv.map.hdb
.............\.............\..\clkdiv.map.logdb
.............\.............\..\clkdiv.map.qmsg
.............\.............\..\clkdiv.pre_map.cdb
.............\.............\..\clkdiv.pre_map.hdb
.............\.............\..\clkdiv.rtlv.hdb
.............\.............\..\clkdiv.rtlv_sg.cdb
.............\.............\..\clkdiv.rtlv_sg_swap.cdb
.............\.............\..\clkdiv.sgdiff.cdb
.............\.............\..\clkdiv.sgdiff.hdb
.............\.............\..\clkdiv.sld_design_entry.sci
.............\.............\..\clkdiv.sld_design_entry_dsc.sci
.............\.............\..\clkdiv.syn_hier_info
.............\.............\..\clkdiv.tan.qmsg
.............\.............\..\clkdiv.tis_db_list.ddb
.............\.............\..\clkdiv.tmw_info
.............\.............\..\prev_cmp_clkdiv.asm.qmsg
.............\.............\..\prev_cmp_clkdiv.fit.qmsg
.............\.............\..\prev_cmp_clkdiv.map.qmsg
.............\.............\..\prev_cmp_clkdiv.qmsg
.............\.............\..\prev_cmp_clkdiv.tan.qmsg
.............\.............\incremental_db\compiled_partitions\clkdiv.root_partition.map.kpt
.............\.............\..............\README
.............\.............\sopc_builder_debug_log.txt
.............\实验一、分频计数实验说明.pdf
.............\clkdivverilog\incremental_db\compiled_partitions
.............\.............\.sopc_builder
.............\.............\db
.............\.............\incremental_db
.............\clkdivverilog
1、分频计数器

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