DDS controller in the FPGA on the realization of Quartus II8.1 use development environment, the use of Altera schematic design, 10-bit width, with dac900

dds_v3_test3
............\address_gen.bsf
............\address_gen.qip
............\address_gen.v
............\address_gen_bb.v
............\address_gen_inst.v

............\address_gen_waveforms.html
............\am_module.bdf
............\am_module.bsf
............\ask_psk.v
............\ask_psk_timer.v
............\bit_cut.bsf
............\bit_cut.v
............\bit_cut.v.bak
............\bit_sel.bsf
............\bit_sel.v
............\Chain1.cdf
............\cpu_0.ocp
............\cpu_0.sdc
............\cpu_0.v
............\cpu_0_ic_tag_ram.mif
............\cpu_0_jtag_debug_module_sysclk.v
............\cpu_0_jtag_debug_module_tck.v
............\cpu_0_jtag_debug_module_wrapper.v
............\cpu_0_mult_cell.v
............\cpu_0_ociram_default_contents.mif
............\cpu_0_oci_test_bench.v
............\cpu_0_rf_ram.mif
............\cpu_0_rf_ram_a.mif
............\cpu_0_rf_ram_b.mif
............\cpu_0_test_bench.v
............\DAC900.bsf
............\DAC_900.v
............\DAC_900.v.bak
............\dac_out.bdf
............\dac_out.bsf
............\data_sel.bsf
............\data_sel.v
............\data_sel.v.bak
............\db
............\..\add_sub_0hj.tdf
............\..\add_sub_2nj.tdf
............\..\add_sub_4oj.tdf
............\..\add_sub_8sj.tdf
............\..\add_sub_atj.tdf
............\..\add_sub_fjj.tdf
............\..\add_sub_hjj.tdf
............\..\add_sub_hkj.tdf
............\..\add_sub_ijj.tdf
............\..\add_sub_jkj.tdf
............\..\add_sub_kkj.tdf
............\..\add_sub_ufj.tdf
............\..\add_sub_vfj.tdf
............\..\altsyncram_1b71.tdf
............\..\altsyncram_1l22.tdf
............\..\altsyncram_27p3.tdf
............\..\altsyncram_3c71.tdf
............\..\altsyncram_47p3.tdf
............\..\altsyncram_67p3.tdf
............\..\altsyncram_9tl1.tdf
............\..\altsyncram_a4p3.tdf
............\..\altsyncram_c4p3.tdf
............\..\altsyncram_c572.tdf
............\..\altsyncram_d5g1.tdf
............\..\altsyncram_e4p3.tdf
............\..\altsyncram_e502.tdf
............\..\altsyncram_egq1.tdf
............\..\altsyncram_f5g1.tdf
............\..\altsyncram_ggq1.tdf
............\..\altsyncram_hg41.tdf
............\..\altsyncram_igq1.tdf
............\..\altsyncram_irf1.tdf
............\..\altsyncram_jrf1.tdf
............\..\altsyncram_qdq1.tdf
............\..\altsyncram_qed1.tdf
............\..\a_dpfifo_8t21.tdf
............\..\a_fefifo_7cf.tdf
............\..\cmpr_5cc.tdf
............\..\cmpr_8cc.tdf
............\..\cmpr_9cc.tdf
............\..\cntr_02j.tdf
............\..\cntr_32j.tdf
............\..\cntr_e0j.tdf
............\..\cntr_fjb.tdf
............\..\cntr_gui.tdf
............\..\cntr_nbi.tdf
............\..\cntr_obi.tdf
............\..\cntr_pbi.tdf
............\..\cntr_qbi.tdf
............\..\cntr_rj7.tdf
............\..\cntr_sbi.tdf
............\..\cntr_tbi.tdf
............\..\cntr_u4j.tdf
............\..\cntr_vbi.tdf
............\..\decode_rqf.tdf
............\..\ded_mult_2o81.tdf
............\..\dffpipe_93c.tdf
............\..\dpram_5h21.tdf
............\..\lpm_add_sub2_add_sub.v

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