A streamlined version of the 32-bit RISC processor, containing the project file xilinx ISE

32bitRISC
.........\32bitRISC
.........\.........\32bitRISC.ise
.........\.........\32bitRISC.ise_ISE_Backup
.........\.........\32bitRISC.ntrc_log
.........\.........\alu.v
.........\.........\cpu.bgn
.........\.........\cpu.bit
.........\.........\cpu.bld
.........\.........\cpu.cmd_log
.........\.........\cpu.drc
.........\.........\cpu.lso
.........\.........\cpu.ncd
.........\.........\cpu.ngc
.........\.........\cpu.ngd
.........\.........\cpu.ngr
.........\.........\cpu.pad
.........\.........\cpu.par
.........\.........\cpu.pcf
.........\.........\cpu.prj
.........\.........\cpu.stx
.........\.........\cpu.syr
.........\.........\cpu.twr
.........\.........\cpu.twx
.........\.........\cpu.ucf
.........\.........\cpu.unroutes
.........\.........\cpu.ut
.........\.........\cpu.v
.........\.........\cpu.xpi
.........\.........\cpu.xst
.........\.........\cpu_map.mrp
.........\.........\cpu_map.ncd
.........\.........\cpu_map.ngm
.........\.........\cpu_pad.csv
.........\.........\cpu_pad.txt
.........\.........\cpu_prev_built.ngd
.........\.........\cpu_summary.html
.........\.........\CPU_TEST.ant
.........\.........\CPU_TEST.jhd
.........\.........\CPU_TEST.tbw
.........\.........\CPU_TEST.tfw
.........\.........\CPU_TEST.xwv
.........\.........\CPU_TEST.xwv_bak
.........\.........\CPU_TEST_beh.prj
.........\.........\CPU_TEST_bencher.prj
.........\.........\CPU_TEST_gen.prj
.........\.........\CPU_TEST_isim_beh.exe
.........\.........\CPU_TEST_tbxr.exe
.........\.........\cpu_usage.xml
.........\.........\cpu_vhdl.prj
.........\.........\decode.v
.........\.........\device_usage_statistics.html
.........\.........\forward.v
.........\.........\io_bus.v
.........\.........\isim
.........\.........\....\work
.........\.........\....\....\alu
.........\.........\....\....\...\alu.h
.........\.........\....\....\...\mingw
.........\.........\....\....\...\.....\alu.obj
.........\.........\....\....\cpu
.........\.........\....\....\...\cpu.h
.........\.........\....\....\...\mingw
.........\.........\....\....\...\.....\cpu.obj
.........\.........\....\....\decode
.........\.........\....\....\......\decode.h
.........\.........\....\....\......\mingw
.........\.........\....\....\......\.....\decode.obj
.........\.........\....\....\forward
.........\.........\....\....\.......\forward.h
.........\.........\....\....\.......\mingw
.........\.........\....\....\.......\.....\forward.obj
.........\.........\....\....\glbl
.........\.........\....\....\....\glbl.h
.........\.........\....\....\....\mingw
.........\.........\....\....\....\.....\glbl.obj
.........\.........\....\....\hdllib.ref
.........\.........\....\....\hdpdeps.ref
.........\.........\....\....\io__bus
.........\.........\....\....\.......\io__bus.h
.........\.........\....\....\.......\mingw
.........\.........\....\....\.......\.....\io__bus.obj
.........\.........\....\....\pc__gen
.........\.........\....\....\.......\mingw
.........\.........\....\....\.......\.....\pc__gen.obj
.........\.........\....\....\.......\pc__gen.h
.........\.........\....\....\ram
.........\.........\....\....\...\mingw
.........\.........\....\....\...\.....\ram.obj
.........\.........\....\....\...\ram.h
.........\.........\....\....\regfile
.........\.........\....\....\.......\mingw
.........\.........\....\....\.......\.....\regfile.obj
.........\.........\....\....\.......\regfile.h
.........\.........\....\....\reg__pipeline
.........\.........\....\....\.............\mingw
.........\.........\....\....\.............\.....\reg__pipeline.obj
.........\.........\....\....\.............\reg__pipeline.h
.........\.........\....\....\rom
.........\.........\....\....\...\mingw

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