SDRAM controller core Verilog implementation。With good referential significance.

hssdrc_latest
.............\trunk
.............\.....\core
.............\.....\....\mt48lc2m32b2.v
.............\.....\....\test.v
.............\.....\doc
.............\.....\...\hssdrc_design_document.pdf
.............\.....\...\hssdrc_design_document_rev10.odt
.............\.....\include
.............\.....\.......\hssdrc_define.vh
.............\.....\.......\hssdrc_tb_sys_if.vh
.............\.....\.......\hssdrc_timescale.vh
.............\.....\.......\hssdrc_timing.vh
.............\.....\.......\tb_define.svh
.............\.....\readme.txt
.............\.....\rtl
.............\.....\...\hssdrc_access_manager.v
.............\.....\...\hssdrc_addr_path.v
.............\.....\...\hssdrc_addr_path_p1.v
.............\.....\...\hssdrc_arbiter_in.v
.............\.....\...\hssdrc_arbiter_out.v
.............\.....\...\hssdrc_ba_map.v
.............\.....\...\hssdrc_data_path.v
.............\.....\...\hssdrc_data_path_p1.v
.............\.....\...\hssdrc_decoder.v
.............\.....\...\hssdrc_decoder_state.v
.............\.....\...\hssdrc_init_state.v
.............\.....\...\hssdrc_mux.v
.............\.....\...\hssdrc_refr_counter.v
.............\.....\...\hssdrc_top.v
.............\.....\sim
.............\.....\...\compile.do
.............\.....\...\sim.do
.............\.....\testbench
.............\.....\.........\hssdrc_driver_class.sv
.............\.....\.........\hssrdc_bandwidth_monitor_class.sv
.............\.....\.........\hssrdc_driver_cbs_class.sv
.............\.....\.........\hssrdc_scoreboard_class.sv
.............\.....\.........\message_class.sv
.............\.....\.........\sdram_agent_class.sv
.............\.....\.........\sdram_interpretator.sv
.............\.....\.........\sdram_transaction_class.sv
.............\.....\.........\sdram_tread_class.sv
.............\.....\.........\tb_prog.sv
.............\.....\.........\tb_top.sv

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