Viterbi decoder source code

Data
....\Input
....\.....\SourceBits.dat
Image
.....\DecodeConsecutiveBlock.pdf
.....\Input2OutputSpect.pdf
RTL
...\clkcntgen.v
...\conv_encoder7.v
...\dff.v
...\FPGA
...\....\LE Model
...\....\........\220MODEL.V
...\....\........\altera_mf.v
...\....\........\apex20ke_atoms.v
...\....\PLL Model
...\....\.........\clkgen1_1.bsf
...\....\.........\clkgen1_1.cmp
...\....\.........\clkgen1_1.inc
...\....\.........\clkgen1_1.v
...\....\.........\clkgen1_1_bb.v
...\....\.........\clkgen1_1_inst.v
...\....\RAM Model
...\....\.........\FPGA
...\....\.........\....\RAMIO48x4.bsf
...\....\.........\....\RAMIO48x4.cmp
...\....\.........\....\RAMIO48x4.inc
...\....\.........\....\RAMIO48x4.v
...\....\.........\....\RAMIO48x4_bb.v
...\....\.........\....\RAMIO48x4_inst.v
...\....\.........\....\RAMIO96x128.bsf
...\....\.........\....\RAMIO96x128.cmp
...\....\.........\....\RAMIO96x128.inc
...\....\.........\....\RAMIO96x128.v
...\....\.........\....\RAMIO96x128_bb.v
...\....\.........\....\RAMIO96x128_inst.v
...\....\.........\....\RAMIO96x32.bsf
...\....\.........\....\RAMIO96x32.cmp
...\....\.........\....\RAMIO96x32.inc
...\....\.........\....\RAMIO96x32.v
...\....\.........\....\RAMIO96x32_bb.v
...\....\.........\....\RAMIO96x32_inst.v
...\....\.........\Initial
...\....\.........\.......\RAM192x128.mif
...\....\.........\Pseudo
...\....\.........\......\RAM192X128.v
...\....\.........\......\RAM384X128.v
...\....\.........\......\RAM384X128_bb.v
...\params.v
...\pDFF.v
...\R16PreTraceBack.v
...\R4ACSArray32.v
...\R4ACSArray32_init.v
...\R4ACSArray32_uninit.v
...\R4BMG.v
...\SurvMEM.v
...\SurvMEM_32.v
...\SurvMEM_48.v
...\SurvMEM_64.v
...\SurvMEM_ramio128.v
...\SurvMEM_ramio32.v
...\TraceBack.v
...\VD_FSM.v
...\viterbi_decoder7.v
SimBench
........\ModelSim
........\........\DebussySignalSet
........\........\................\PostSim.rc
........\........\................\SurvMEM.rc
........\........\................\TestBench.rc
........\........\fsdb
........\........\....\TraceBack.fsdb
........\........\....\ViterbiPostSim.fsdb
........\........\....\ViterbiRTLSim.fsdb
........\........\....\ViterbiRTLSim_SyncRAM.fsdb
........\........\Testbench.v
........\........\ViterbiSim.mpf
........\........\work
........\........\....\@p@r@i@m_@d@f@f@e
........\........\....\.................\verilog.asm
........\........\....\.................\_primary.dat
........\........\....\.................\_primary.vhd
........\........\....\@testbench
........\........\....\..........\verilog.asm
........\........\....\..........\_primary.dat
........\........\....\..........\_primary.vhd
........\........\....\and1
........\........\....\....\verilog.asm
........\........\....\....\_primary.dat
........\........\....\....\_primary.vhd
........\........\....\and16
........\........\....\.....\verilog.asm
........\........\....\.....\_primary.dat
........\........\....\.....\_primary.vhd
........\........\....\apex20ke_asynch_io
........\........\....\..................\verilog.asm
........\........\....\..................\_primary.dat
........\........\....\..................\_primary.vhd
........\........\....\apex20ke_asynch_lcell
........\........\....\.....................\verilog.asm

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