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Reactive Power Compensation Downloaded：0: Matlab Simulink Reactive Power Compensation files
Update : 2021-09-17 Size : 9.54kb Publisher : ahmed58bn@gmail.com
DC Microgrid Demo Downloaded：1: let's enjoy Matlab Simulink DC Microgrid Demo
Update : 2021-09-17 Size : 1000.38kb Publisher : ahmed58bn@gmail.com
power flow calculation polar coordinates, with IEEE14 nodes, 30 nodes Downloaded：0: Matlab power flow calculation polar coordinates, with IEEE14 nodes, 30 nodes package
Update : 2021-09-17 Size : 14.86kb Publisher : ahmed58bn@gmail.com
model Simulink of Arduino Downloaded：0: enjoy model Simulink of Arduino
Update : 2021-09-17 Size : 391.07kb Publisher : ahmed58bn@gmail.com
Loterias Quina Downloaded：0: Brazil lottery with analysis
Update : 2021-09-25 Size : 11.93mb Publisher : pizcol@gmail.com
Optimal Power Flow using PSO Downloaded：0: Optimal Power Flow using PSO in MATLAB platform.
Update : 2021-09-27 Size : 13.86kb Publisher : faraji.project@gmail.com
CH341A Downloaded：0: CH341A SOURCE CODE. THIS IS CH341 PROGRAMMER SOFTWARE SOURCE CODE
Update : 2021-10-05 Size : 1.59mb Publisher : kasunlive
CAD algorithms for circuit layouts Downloaded：0: Source codes: src/cse788_layout.c - Code transform netlist output into magic file src/cse788_netlist.c - Implementation of optimzal netlist solver src/cse788_gordian.c - Implementation of gordian placement algorithm src/
Update : 2021-10-25 Size : 193.26kb Publisher : nalevihtkas
Technology Mapping : VLSI Downloaded：0: Input format: GraphML : graphml format contains nodes and edges of the graph. Output format: Testing: Done by VLSI TEAM
Update : 2021-10-25 Size : 57.58kb Publisher : nalevihtkas
VLSI CAD ALGORITHMS Downloaded：0: Algorithms and data structures: efficient representation of graphs; Elementary graph algorithms involving bfs and dfs trees, such as finding connected and 2- connected components of a graph, the minimum spanning tree, sh
Update : 2021-10-25 Size : 274.53kb Publisher : nalevihtkas
A Maze Router Downloaded：0: An algorithm to route the wires in integrated circuits. The router handles 2 point nets, non-unit costs in the routing grid, bend penalties and uses 2 separate routing layers.
Update : 2021-10-25 Size : 52.62kb Publisher : nalevihtkas
Domain Specific Hardware Accelerators: Vector Processing Units Downloaded：0: This repository contains the source code for VLSI CAD Project, Domain Specific Hardware Accelerators, as apart of coursework in CS6230 : CAD for VLSI. Fall, 2020. What does this repo enclose? Overview The following compo
Update : 2021-10-25 Size : 3.15mb Publisher : nalevihtkas

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