VHDL-FPGA-Verilog List Page 935

VHDL-FPGA-Verilog list

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divfrequency Downloaded：0: verilogHDL program successfully achieve divide
Date : 2025-08-02 Size : 142kb User : 张超
ALU Downloaded：0: FPGA-based implementation of a simple ALU. ALU mainly contains symbols of addition, subtraction, multiplication, left, right. To control the operation of the ALU and reset the top.
Date : 2025-08-02 Size : 680kb User : 非南
inequal-lenghth-code Downloaded：0: Unequal-length coding design, Morse code improvements, using vhdl
Date : 2025-08-02 Size : 14.97mb User : 非南
excess-3-code-adder-subtructer Downloaded：0: I 3 yards excess-3 code adder and subtractor using vhdl
Date : 2025-08-02 Size : 4.94mb User : 非南
16-bit-binary-full-adder Downloaded：0: 16-bit binary full adder
Date : 2025-08-02 Size : 1kb User : peter
MIAODZQ Downloaded：0: electronic keyboard
Date : 2025-08-02 Size : 86kb User : 缪照浜
ZRtech-PERI7-LCM Downloaded：0: Based on the NIOS II LCM driver development, including TFT 9325 driven learning, LCD color bar display, SD card drive, simple digital photo frame, driving touch
Date : 2025-08-02 Size : 25.18mb User : liju
man2uart_latest.tar Downloaded：0: fpga uart ip core
Date : 2025-08-02 Size : 2kb User : Aden
LC3_CPU Downloaded：0: lc3 cpu lc3 cpulc3 cpu
Date : 2025-08-02 Size : 9kb User : wenjie
LabA1Design2 Downloaded：0: Design pattern comparator circuit: circuit input as two 8-bit unsigned binary numbers a, b and a mode control signal m circuit output is 8-bit unsigned binary number y. When when m = 0, y = MAX (a, b) and when m = 1, the
Date : 2025-08-02 Size : 1kb User : Peter
LabA1Design1 Downloaded：0: Design for the number two absolute value of the difference between circuits: circuit input aIn, bIn a 4-bit unsigned binary number, the circuit output out of the absolute value of the difference between the two numbers,
Date : 2025-08-02 Size : 3kb User : Peter
music_player Downloaded：1: Modelsim and FPGA-based music player
Date : 2025-08-02 Size : 21kb User : Peter

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