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con_addr_32

  • Category : VHDL-FPGA-Verilog
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  • Update : 2013-11-01
  • Size : 2kb
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  • Author :Pe***
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Introduction - If you have any usage issues, please Google them yourself
Because binary adder carry only be 1 or 0, so it can be 32-bit adder is divided into eight (minimum one by the four carry-lookahead adder directly constitute the remaining adder structures using carry-lookahead adder structure), respectively Addition calculation, in addition to other than the lowest seven two copies of each adder structure, carry input is scheduled for 1 and 0, respectively. Thus, the adder 8 can be performed simultaneously the respective adder, and then the respective adjacent low addition result generated carry bit output, select the correct output of the addition result.
Packet file list
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src\addr_forward_4.v
...\addr_forward_4_tb.v
...\addr_sel_4.v
...\con_addr_32.v
...\con_addr_32_tb.v
...\mux_4.v
src
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