VHDL-FPGA-Verilog List Page 784

VHDL-FPGA-Verilog list

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work Downloaded：0: Digital system design and use of the VHDL code lesson is easy to confuse
Date : 2025-07-06 Size : 3.62mb User : 钟晓辉
LCD_Display_kb Downloaded：0: This VHDL Code express how can you connect an LCD To FPGA Spartan 3ee
Date : 2025-07-06 Size : 3kb User : Ezrashafiez
1_traffic_light Downloaded：0: Traffic lights verilog code
Date : 2025-07-06 Size : 2kb User : 项中元
FIFO Downloaded：0: FIFO, FIFO buffer, verilog source code, including test code.
Date : 2025-07-06 Size : 2kb User : 项中元
LIFO Downloaded：0: LIFO, last-out buffer (stack), verilog source code, including test code.
Date : 2025-07-06 Size : 2kb User : 项中元
ALU Downloaded：0: ALU, two types of verilog source code, including test code, originality.
Date : 2025-07-06 Size : 5kb User : 项中元
32FIRVHDL Downloaded：0: 32 order FIR digital filter based on FPGA design source program. Design USES parallel multiplier, faster and less memory, less delay.
Date : 2025-07-06 Size : 2kb User : wanzhenyuan
pid-vhdl Downloaded：0: Pid controller based on VHDL design, can use the quartus software implementation, etc. Digital pid control system design of source co
Date : 2025-07-06 Size : 70kb User : wanzhenyuan
FPGA--FIR--bishe Downloaded：1: A reference of the graduation design paper, adjustable parameters of digital filter. Have detailed introduces, the principle of the design source program and the simulation process and result
Date : 2025-07-06 Size : 1.32mb User : wanzhenyuan
efuse_ctrl Downloaded：0: E-fuse controller for TSMC 0.16um
Date : 2025-07-06 Size : 4kb User : 林文榮
i2c_slave Downloaded：0: I2C interface slave tape out verification ok
Date : 2025-07-06 Size : 3kb User : 林文榮
if_3w Downloaded：0: 3-wire interface slave tape out verification ok
Date : 2025-07-06 Size : 1kb User : 林文榮

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