VHDL-FPGA-Verilog List Page 783

VHDL-FPGA-Verilog list

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CPU Downloaded：0: CPU-design VHDL
Date : 2025-07-06 Size : 290kb User : lxd
SPWM Downloaded：0: As can be seen based SPWM pulse voltage and current waveforms under simulink simulation and harmonic analysis by FFT
Date : 2025-07-06 Size : 8kb User : sunrain
FIR Downloaded：0: Write VHDL FIR filter, front end DDS generated wave source
Date : 2025-07-06 Size : 5.16mb User : huag
ShanYu Downloaded：0: Change the procedure for puncturing procedure, which can be achieved punctured 3/4, 2/3 of the function, and by QUARTUS II software compiler.
Date : 2025-07-06 Size : 297kb User : 旭阳
verilog-0.9.7.tar Downloaded：0: iverilog 0.9.7
Date : 2025-07-06 Size : 1.18mb User : wise wang
NIOSII Downloaded：0: Soft-core with NoisII timing and realization of ultrasonic distance measurement 485
Date : 2025-07-06 Size : 9.48mb User : XiaoV
anjian2 Downloaded：0: EP2C35F Series development board on key debounce mechanical experiments, testing, simulation code
Date : 2025-07-06 Size : 2.77mb User : 陈坤
LGFXY Downloaded：0: EP2C35F Series development board on simple logic analyzer design, simulation, use an external ADC chip
Date : 2025-07-06 Size : 6.6mb User : 陈坤
szxszw Downloaded：0: Digital clock (4) the timing of the display and will now be displayed with full set of clock function very well designed, clear design hierarchy
Date : 2025-07-06 Size : 424kb User : 恒
uart_verilog.tar Downloaded：0: The experimental UART on FPGA verilog source
Date : 2025-07-06 Size : 1kb User : libaizhang
lcd_i80_verilog.tar Downloaded：0: In the FPGA i80 (intel 8080) interface to the LCD driver verilog source.
Date : 2025-07-06 Size : 1kb User : libaizhang
Multiply8-6 Downloaded：0: FPGA verilog With shift and add a way to achieve 8 multiplier
Date : 2025-07-06 Size : 232kb User : 李潇

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