VHDL-FPGA-Verilog List Page 64

VHDL-FPGA-Verilog list

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Xilinx开发板初学者问题总结 Downloaded：0: Summary of problems encountered in the development of XILINX series FPGA
Date : 2025-05-14 Size : 747kb User : 鱼在在藻
9516 Downloaded：0: 9516 register configuration, there is a detailed English note, easy to understand, worth a look at
Date : 2025-05-14 Size : 5kb User : 1234李四
方案二 Downloaded：0: This system is a CPLD microcontroller for signal frequency and period, time interval and the duty ratio of digital frequency measurement meter based on the system by the AGC (automatic gain control) circuit, amplifier ci
Date : 2025-05-14 Size : 76kb User : 小竹丶
7f8da115f83d72b263e5818b9374e466 Downloaded：0: PLL configuration using FPGA IN VERILOG LANGUAGE FOR BEGINNER
Date : 2025-05-14 Size : 1.55mb User : nassrou
08167129pllverilog Downloaded：0: PLL CONFIGUARTION USING FOAGA IN VERILOG LANGUAGE
Date : 2025-05-14 Size : 192kb User : nassrou
17416335PLLfpgapaper Downloaded：0: PLL CONFIGURATION USING FPGA IN VERILOG LANGUAGE
Date : 2025-05-14 Size : 280kb User : nassrou
31767694FPGA-PLL Downloaded：0: PLL CONFIGURATION USING FPGA
Date : 2025-05-14 Size : 324kb User : nassrou
37148515LC Downloaded：0: PLL CONFIGUARTION USING FPGA
Date : 2025-05-14 Size : 286kb User : nassrou
aes-master Downloaded：0: aes master by vhdl code and decode
Date : 2025-05-14 Size : 67kb User : Nguyen Nam
aes128-hdl-master Downloaded：0: Verilog AES hdl key 128 bit code and decode
Date : 2025-05-14 Size : 836kb User : Nguyen Nam
aes-project-master Downloaded：0: aes project vhdl FPGA
Date : 2025-05-14 Size : 1.05mb User : Nguyen Nam
counter Downloaded：0: Code based on FPGA, a realization of VHDL/counter
Date : 2025-05-14 Size : 24kb User : yida008

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