VHDL-FPGA-Verilog List Page 627

VHDL-FPGA-Verilog list

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fir_noRom Downloaded：0: desgin the 16 bits FIR Filter by VHDL
Date : 2025-06-25 Size : 4.89mb User : 林嘉英
tt Downloaded：0: python t_wave_53.py reads ../lena_256.png to generate m then reads lena256.hex writes test1_256_fwt.png and test1_256_iwt.png
Date : 2025-06-25 Size : 307kb User : Edward
signal-generator Downloaded：0: Advanced experimental _16_DA [DA9708] : output sine, square, triangle, sawtooth (frequency, amplitude adjustable)
Date : 2025-06-25 Size : 1.92mb User : FLL
keyboard-tube Downloaded：0: Advanced experimental _09_PS2_02: receiving standard keyboard input, displayed on the digital tube
Date : 2025-06-25 Size : 627kb User : FLL
MedianFilter33 Downloaded：0: Debugging that median filtering program
Date : 2025-06-25 Size : 59kb User : FLL
VGA Downloaded：0: Advanced experimental _05_VGA: through the VGA display a Chinese characters, 800 x600 @ 72 hz
Date : 2025-06-25 Size : 1.28mb User : FLL
1602 Downloaded：0: _04_LCD1602 advanced experiment shows: on the LCD1602 display RedCore url
Date : 2025-06-25 Size : 290kb User : FLL
Verilog-example1 Downloaded：0: verilog examples to explain, a classic example of the analysis, can effectively help beginners.
Date : 2025-06-25 Size : 35kb User : lyon
Verilog-example2 Downloaded：0: verilog examples to explain the second part, to further expand on the basics of the application, by an example to help you understand verilog
Date : 2025-06-25 Size : 24kb User : lyon
Verilog-example3 Downloaded：0: The third case study verilog part, by an example to explain the finite state machine design process.
Date : 2025-06-25 Size : 1.48mb User : lyon
MastersThesisPreliminaryReport Downloaded：0: developmentof a reconfigurable muti-protocol verification environment using uvm methodology
Date : 2025-06-25 Size : 152kb User : 王小米
tlm Downloaded：0: OSCI TLM 2.0 KIT UNIT TEST DEMO
Date : 2025-06-25 Size : 159kb User : 王小米

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