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VHDL-FPGA-Verilog list
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Verilog description of the serial port, receive data, send data using the trigger button
Date : 2025-06-24 Size : 2kb User : MR_shang

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SPI for AD5623
Date : 2025-06-24 Size : 9.41mb User : xiadafang

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About convolution coding MATLAB language code and Viterbi decoding
Date : 2025-06-24 Size : 9kb User : wss

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verilog miiller codecs, including test banch file
Date : 2025-06-24 Size : 2kb User : Sichengkiu

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OneSpin training material is used to study assertion verification in ASIC design.
Date : 2025-06-24 Size : 18.72mb User : Xihu

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OneSpin training material can help user study assertion verification method in ASIC design.
Date : 2025-06-24 Size : 14.35mb User : Xihu

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OneSpin training material can help user understand how to do assertion verification in ASIC design.
Date : 2025-06-24 Size : 9.27mb User : Xihu

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The serial input into parallel output to serial or parallel input output process. Capable of serial received a 1 or 0 character, every 8 sequentially (first received at a low) arranged in an 8-bit byte output. To ensure
Date : 2025-06-24 Size : 256kb User : 123

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This experiment is completed weighted mean filter, which works as follows: Set data collected by the beat input, in turn represented as d0, d1, d2, d3, d4, ..., the output order of do = d0* 1/4+ d1* 1/2+ d2* 1/4 do = d1*
Date : 2025-06-24 Size : 378kb User : 123

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A Celsius temperature to complete the (integer) into circuit Fahrenheit, relations are as follows: F = C*9/5+32
Date : 2025-06-24 Size : 347kb User : 123

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The completion of the 3 3 bit multipliers, the multiplication problem is transformed into a logic and operation and the addition operation.
Date : 2025-06-24 Size : 262kb User : 123

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Implement 5 people vote, and the timing and voting results show.
Date : 2025-06-24 Size : 1kb User : xiaoyuhan
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