VHDL-FPGA-Verilog List Page 535

VHDL-FPGA-Verilog list

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uart_server Downloaded：0: 24 way serial ports to 1 serial port, including FIFO module,RX module,TX module, timer module, detection and control module, etc.. Verilog preparation
Date : 2025-06-21 Size : 371kb User : wangyu
m6502 Downloaded：0: m6502 6 bit microprocessor
Date : 2025-06-21 Size : 798kb User : Zero
fistnoc Downloaded：0: VHDL CODE, WILL GIVE DESIGN ABOUT NETWORK ON CHIP
Date : 2025-06-21 Size : 8.41mb User : elango
Nixietube_count Downloaded：0: count number in nixie tube
Date : 2025-06-21 Size : 330kb User : 李强
Caculator Downloaded：0: Verilog language based on simple calculator, to achieve the operation of addition and subtraction, there are modules and constraint files.
Date : 2025-06-21 Size : 13kb User : 杨逍
verilog_code_for_double_fpu Downloaded：0: 64-bit FPU, embedded testbench, simulation has been validated.
Date : 2025-06-21 Size : 115kb User : 张邈
HAPF_SLAVE2 Downloaded：1: SVG high voltage chain of verilog FPGA control procedures, including SPI, 16 road SCI synchronous communication module procedures to protect the self-locking function program, based on the detection and reactive power co
Date : 2025-06-21 Size : 17kb User :
iic Downloaded：0: i2c interface function implementation code, written in VERILOG, along with testbench
Date : 2025-06-21 Size : 522kb User : jianglei
uart Downloaded：0: Serial implementation code written using verilog, together with simulation files.
Date : 2025-06-21 Size : 978kb User : jianglei
sdram_mdl Downloaded：0: SDRAM-based literacy commissioning tests, using verilog language, through debugging.
Date : 2025-06-21 Size : 2.18mb User : jianglei
fenpin Downloaded：1: The program is the input clock frequency, here is changing the division multiples, this is one eighth the frequency of the program
Date : 2025-06-21 Size : 253kb User : 孙乐
YCbCr_camera Downloaded：0: Image format conversion
Date : 2025-06-21 Size : 14.38mb User : 刘强

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