VHDL-FPGA-Verilog List Page 486

VHDL-FPGA-Verilog list

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UART_TEST Downloaded：0: this is FPGA Verilog project
Date : 2025-06-19 Size : 3.31mb User : TaeKiHong
fnd-clk Downloaded：0: FND, SEGment verilog code
Date : 2025-06-19 Size : 2kb User : TaeKiHong
Read_SPI_ADC Downloaded：0: This VHDL code takes a clock, reset, Capture_EN and SPI data LT2315 ADC and generates SPI_CLK and SPI_nCS of it and reads 12-bit serial data ADC and returns 12-bit parallel data.
Date : 2025-06-19 Size : 1kb User : Hossein
altera-TimeQuest_User_Guide Downloaded：0: altera timing handbook，directly got xilinx.
Date : 2025-06-19 Size : 3.76mb User : 程云
xilinx-tcl Downloaded：0: Xilinx tcl handbook, directly got Xilinx。
Date : 2025-06-19 Size : 2.45mb User : 程云
i2c_master_top Downloaded：0: The function description of I2C bus top level
Date : 2025-06-19 Size : 2kb User : Luke
i2c_master_bit_ctrl Downloaded：0: I2C control bus master, according to the byte write verilog code design, because the option is not verilog this, so choose VHDL
Date : 2025-06-19 Size : 2kb User : Luke
i2c_master_byte_ctrl Downloaded：0: I2C control bus according to the word write and write functions implemented by host verilog
Date : 2025-06-19 Size : 1kb User : Luke
i2c_slave_model Downloaded：0: I2C bus control heavy machine model, used to verify whether the design implements I2C Functional Description
Date : 2025-06-19 Size : 2kb User : Luke
tst_bench_top Downloaded：0: I2C control bus test platform testbench, used to verify the correctness of the interaction I2C master impact
Date : 2025-06-19 Size : 2kb User : Luke
VHDL-Gray-code Downloaded：0: Gray code design based on VHDL code, debugging didn t mistake.
Date : 2025-06-19 Size : 91kb User : 谢正伟
pwm Downloaded：0: A pulse width modulation pwm template, because it is learning to use, increasing the data input for viewing experimental phenomena in the development board led lamp, the greater the greater the luminance of the input dat
Date : 2025-06-19 Size : 2.89mb User : 邓智浩

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