VHDL-FPGA-Verilog List Page 482

VHDL-FPGA-Verilog list

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traffic Downloaded：0: vhdl achieve control of traffic lights, with pedestrian priority principle, the greatest degree of real-time monitoring
Date : 2025-06-19 Size : 20kb User : 赵宁
14.3 Downloaded：0: xilinx app1026 关于Ethernet的使用例程
Date : 2025-06-19 Size : 17.05mb User : zhangsong
2_Qsys_Intro_Lab Downloaded：0: max10 led demo，using tcl to run
Date : 2025-06-19 Size : 12kb User : liuluren
3_Embedded_Systems_Lab Downloaded：0: max10 demo，Lab3 Embedded Systems Lab
Date : 2025-06-19 Size : 233kb User : liuluren
4_Gesture_Sensor_Lab Downloaded：0: altera max10 Lab4 Gesture Sensor Lab，carry out with nios2
Date : 2025-06-19 Size : 61kb User : liuluren
5_ADC_Lab Downloaded：0: altear max 10 demo with 2 adc， max support 18 channel adc
Date : 2025-06-19 Size : 50kb User : liuluren
6_USB_to_SDHC_Lab Downloaded：0: altera max10 USB demo，using PHY device，design a U pan
Date : 2025-06-19 Size : 2.12mb User : liuluren
7_BLE_WIFI_Lab Downloaded：0: altera max10 wifi demo，it is very usefull wo designers
Date : 2025-06-19 Size : 2.47mb User : liuluren
8_MIPI_to_HDMI_Terasic Downloaded：0: altera max10 mipi demo，using mipi ip core，but it need lic file. HDMI also be use in the design and it is useful for video development
Date : 2025-06-19 Size : 1.18mb User : liuluren
RS485 Downloaded：0: FPGA/CPLD realize RS485 communication protocol used to Verilog simulation on Quartus ii programming platform
Date : 2025-06-19 Size : 654kb User : cyl
FPGA-program-flow-chart Downloaded：0: altera fpga
Date : 2025-06-19 Size : 107kb User : gone
URAT-VHDL Downloaded：0: uart vhdl rx/tx
Date : 2025-06-19 Size : 32kb User : gone

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