VHDL-FPGA-Verilog List Page 454

VHDL-FPGA-Verilog list

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first_zynq_design Downloaded：0: zedboard vhdl code to control led on the board
Date : 2025-12-31 Size : 23mb User : 无尽
FIR.ip Downloaded：0: code to implement the FIR function on zedboard
Date : 2025-12-31 Size : 22kb User : 无尽
SoCKit_Audio Downloaded：0: SoCKit_Audio，使用SoCKit FPGA开发板，使用SSM2603视频编码ADC芯片，进行视频传输处理，使用verilog语言。
Date : 2025-12-31 Size : 3.75mb User : jiangkun
High-level-synthesis Downloaded：0: powrpoint format document about high-level synthesis ,including concetpions,flows ,examples
Date : 2025-12-31 Size : 2.78mb User : wang bo
High-Level-Design-with-SystemC Downloaded：0: high-level synthesis with system C language,this document intoduce concetps,methods and flow
Date : 2025-12-31 Size : 63kb User : wang bo
sch Downloaded：0: electronic system level HLS design, cpp code for scheduling
Date : 2025-12-31 Size : 2kb User : wang bo
H.264-for-FPGA Downloaded：0: This Book describe about H.264 encoder using Verilog HDL
Date : 2025-12-31 Size : 13.1mb User : jhojho
Exercising-H.264-Video-Compression-IP-Using-Comme Downloaded：0: This book describe about Exercising-H.264-Video-Compression-IP-Using-Commer.
Date : 2025-12-31 Size : 742kb User : jhojho
MTM_UEC1_lab04_raportfinalny Downloaded：0: verilog hdl BCD to 7seg converter with testing module
Date : 2025-12-31 Size : 547kb User : ocmob
uart_mm Downloaded：0: Its uart transmitter and receiver
Date : 2025-12-31 Size : 3.35mb User : trung
DDR3-SDRAM-Verilog-Model Downloaded：0: Date : 2025-12-31 Size : 69kb User : 刘建
dwn_sampler Downloaded：0: Multirate digital signal processing system which includes sampling rate conversion. This technique is necessary for systems with different input and output sampling rates, as the proposed multirate device is downsampler
Date : 2025-12-31 Size : 2kb User : Mohan Reddy

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