VHDL-FPGA-Verilog List Page 449

VHDL-FPGA-Verilog list

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AnJian_1602 Downloaded：1: Calculator design. Using a field programmable logic device FPGA design, VHDL language based on arithmetic function, and decimal display on the digital tube. Computing part adder, subtraction, multiplier and divider compo
Date : 2025-06-17 Size : 12.53mb User : 陈勒
ZX_SOPC0 Downloaded：0: DDS source FPGA-based design 1. The output signal is a sine wave, triangle spread pulse 2. The signal amplitude adjustable range: 1V ~ 5V 3. AM step: 10mV The signal frequency is low frequency: 10HZ ~ 1MHZ 5. Frequency a
Date : 2025-06-17 Size : 8.64mb User : 陈勒
booth_mult Downloaded：0: 4* 4 booth multiplier design, test module has been validated, there are notes, useful in understanding the booth multiplier principle.
Date : 2025-06-17 Size : 3kb User : 荣志强
risc8_cpu_verilog Downloaded：0: The example design of RISC-CPU bus architecture uses a data line (8) and command line (12) is separated with the Harvard architecture, the storage register addressing uses RAM as a register to facilitate programming.
Date : 2025-06-17 Size : 611kb User : 荣志强
qnr_verilog Downloaded：0: Rounding quantization internal QNR includes a divider module and generates data output valid and circulating the results to the nearest integer circuit, including the simulation results shown in Fig.
Date : 2025-06-17 Size : 813kb User : 荣志强
DCT_verilog Downloaded：0: DCT is a digital image processing a basic algorithm to achieve the conversion the time domain to the frequency domain, and thus remove the domain relevance of data in favor of the quantized transform coefficients using r
Date : 2025-06-17 Size : 496kb User : 荣志强
DES_verilog Downloaded：0: Using DES (Data Encryption Standard Data Encryption Standard) verilog to achieve, the 64 plaintext input into 64 output ciphertext block.
Date : 2025-06-17 Size : 466kb User : 荣志强
uart_lcd_display_XUP Downloaded：0: Date : 2025-06-17 Size : 1.05mb User : queen
an181_2_2 Downloaded：0: Excalibur Solutions— Multi-Master Reference Design
Date : 2025-06-17 Size : 804kb User : 固永
fft1024-verilogCODE Downloaded：0: fftpoint 1024 verilog code
Date : 2025-06-17 Size : 51kb User : tao
rcvr Downloaded：0: verilog serial port to receive the program, there are detailed notes, suitable for learning
Date : 2025-06-17 Size : 1kb User : 吕攀攀
N-DtoA-VHDL-AMS Downloaded：0: The following is an example of a mixed signal that is a N bit D/A converter described in VHDL-AMS
Date : 2025-06-17 Size : 7kb User : 杜子腾

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