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mu0
Downloaded:0
Based on a simple CPU Xilinx Spartan6 of MU0 VHDL
Date
: 2025-06-17
Size
: 1.15mb
User
:
康二栋1号
11-songer
Downloaded:0
Play Lovers of FPGA-based Xilinx Spartan6 case program VHDL
Date
: 2025-06-17
Size
: 257kb
User
:
康二栋1号
RISC_CPU
Downloaded:0
Graduation design, development board based on Xilinx Spartan6 homemade experiment. Graduation design, to achieve a simple calculator. VHDDL
Date
: 2025-06-17
Size
: 1.77mb
User
:
康二栋1号
8-TFT_24
Downloaded:0
Development board based on Xilinx Spartan6 homemade experiment, 2.4 TFT screen kept static refresh specific picture. If you want to modify the picture, the image is generated using Matlab* .coe format, generate ROM loade
Date
: 2025-06-17
Size
: 1.28mb
User
:
康二栋1号
TSMC
Downloaded:1
TCBN65LPBWP7T VERSION 200A tsmc CLN65LP : 65nm CMOS LOGIC Low Power
Date
: 2025-06-17
Size
: 20.47mb
User
:
pong hk
fifo
Downloaded:0
The realization of the asynchronous FIFO, very classic three-step writing state machine.
Date
: 2025-06-17
Size
: 1kb
User
:
孙金傲
clock
Downloaded:0
Use verilog digital clock
Date
: 2025-06-17
Size
: 1kb
User
:
孙金傲
spi
Downloaded:0
Use verilog implementation of spi interface simple small program, suitable for beginners to learn.
Date
: 2025-06-17
Size
: 1kb
User
:
孙金傲
compare
Downloaded:0
Use verilog implementation file input comparator, if the input data at the same time the same output high level, otherwise the output low level, to achieve the effect of alignment.
Date
: 2025-06-17
Size
: 1kb
User
:
孙金傲
changewin
Downloaded:0
Use verilog implementation 40 bits of string and transform, incentive documents written in a program at the same time.
Date
: 2025-06-17
Size
: 1kb
User
:
孙金傲
ELECTRONICCLOCK
Downloaded:0
VHDL language design electronic clock, and there is a pause function and achieve clear function buttons, and with stopwatch
Date
: 2025-06-17
Size
: 6kb
User
:
安迪
sixty_test1
Downloaded:0
count sixty
Date
: 2025-06-17
Size
: 234kb
User
:
veruslana
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