VHDL-FPGA-Verilog List Page 4239

VHDL-FPGA-Verilog list

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pinlvji Downloaded：0: the frequency meter is measuring weeks, frequency measurement, measuring the ratio of the basic functions can automatically shift error of 1%
Date : 2025-08-12 Size : 639kb User : 马忠志
[eda]vhdl Downloaded：0: Fuzhou University EDA optional courses in all experimental code. VHDL description (vhd), and circuit (GdF)
Date : 2025-08-12 Size : 217kb User : 林锋杰
Evita_Verilog Downloaded：0: Verilog very handy and easy to teaching software.
Date : 2025-08-12 Size : 3.6mb User : 王虎林
Evita_VHDL Downloaded：0: VHDL very handy and easy to teaching software. We try.
Date : 2025-08-12 Size : 2.86mb User : 王虎林
CPLD_DMA Downloaded：0: This is a ISP1582 USB device DMA transmission of the auxiliary circuit hardware design source code
Date : 2025-08-12 Size : 5kb User : 张国梁
RAMINCREASE Downloaded：0: CPLD This is done using the DSP memory expansion of the source document.
Date : 2025-08-12 Size : 6kb User : 张国梁
primetime Downloaded：0: This is the VHDL language delay the test procedure used to determine the performance CPLD
Date : 2025-08-12 Size : 51kb User : 张国梁
mt48lc2m32b2 Downloaded：0: SDRAM control nuclear, has been tested, we can use a slightly modified
Date : 2025-08-12 Size : 9kb User : 洪戈
SDRAM_C Downloaded：0: SDRAM control core has been tested and can be modified with a slight modification. It has been tested, we can use a slightly modified
Date : 2025-08-12 Size : 1kb User : 洪戈
time_clock Downloaded：0: practical alarm the Verilog code. VHDL is not! After certification ldv
Date : 2025-08-12 Size : 4kb User : 徐哦俄
cal_verilog Downloaded：0: calculator chips to achieve the Verilog code! Timing simulation success
Date : 2025-08-12 Size : 6kb User : 徐哦俄
Verilog-statemachine Downloaded：0: use Verilog Programming state machine example. Very good.
Date : 2025-08-12 Size : 179kb User : 张厂

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