VHDL-FPGA-Verilog List Page 4224

VHDL-FPGA-Verilog list

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plane_game Downloaded：0: this as a preparation using VHDL hardware Games, 16* 16 in the lattice achieving an aircraft game, it could have aircraft and the aircraft can escape to. Quite interesting.
Date : 2025-05-16 Size : 47kb User : 万广鲁
Push_Boxes Downloaded：0: Xilinx environment in the preparation of the VHDL program, realized the game viewing tasks, the interface is very beautiful.
Date : 2025-05-16 Size : 6kb User : 吴倩茜
cordic_beh Downloaded：0: This is the algorithm Coordinate rotation digital source, the documents of the internal documents can be found in the Notes.
Date : 2025-05-16 Size : 28kb User : 喻小星
A8251 Downloaded：0: 8251 port initialization definition includes 13 input ports and output ports 9
Date : 2025-05-16 Size : 2kb User : 孤独王子
EDAchuzuchejijia Downloaded：0: in this sample program, using VHDL of the entry price of a taxi function, in preparation FLEX10K environment, through cpld download plate to the verification process. The compression package with the purpose of example,
Date : 2025-05-16 Size : 332kb User : bkd
cpldcontrol Downloaded：0: a cpld control procedures can be done- and switching to read and write interface per second 64k
Date : 2025-05-16 Size : 2kb User : 徐泯
addsub_core_ Downloaded：0: HDL 8051 nuclear, we know that is really useful to try it. Xilinx's nuclear
Date : 2025-05-16 Size : 1kb User : 徐泯
addsub_cy_ Downloaded：0: Adder nuclear, into place at the company's nuclear Xilinx can use
Date : 2025-05-16 Size : 1kb User : 徐泯
youxiufft Downloaded：0: 16:00 fft the procedure. Very good, compilers have achieved, or good
Date : 2025-05-16 Size : 287kb User : 席鹏飞
8051VHDL Downloaded：0: C8051 core of a VHDL source code
Date : 2025-05-16 Size : 411kb User : ydx
ccpu Downloaded：0: this is a done VERILOG eight functional weak CPU
Date : 2025-05-16 Size : 16kb User : 贾振华
pluse_delay Downloaded：0: using VHDL-trigger circuit stability, steady time for the whole system clock several times.
Date : 2025-05-16 Size : 87kb User : david

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