VHDL-FPGA-Verilog List Page 4221

VHDL-FPGA-Verilog list

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usb_funct.tar Downloaded：0: usb_funct is used for usb with 400MHz.
Date : 2025-05-16 Size : 193kb User :
jpeg.tar Downloaded：0: JPEG is used for visual digit telephone and al camera.
Date : 2025-05-16 Size : 3.26mb User :
binary_to_bcd.tar Downloaded：0: binary_to_bcd is used for translating fro m binare to bcd.
Date : 2025-05-16 Size : 44kb User :
cpld-download-cable-tuzi Downloaded：0: cpld download cable detailed drawings and descriptions, 244 realization, stable, good speed.
Date : 2025-05-16 Size : 4.09mb User : mengzi
detector Downloaded：0: the program eight Sequence Detection functions.
Date : 2025-05-16 Size : 5kb User : 123
fdpll Downloaded：0: simple configurable dpll VHDL code. Clock Recovery for the jitter filtering is a very good result, but can pll configuration parameters of the series.
Date : 2025-05-16 Size : 2kb User : 陈德炜
vhdll Downloaded：0: 8421BCD code input and output for 8421BCD yards. Procedures for automatic input conversion, will be converted into 8421BCD I 3 yards, and then use that function to achieve additive, the use of procedures and the results
Date : 2025-05-16 Size : 42kb User : oy
FPGA_LMS Downloaded：1: VHDL LMS algorithm written procedures. The use of local sinusoidal signal, according to the LMS algorithm for tracking the input signal. Used to produce and the input signal with frequency phase with the local signal.
Date : 2025-05-16 Size : 264kb User : 黄鹤
training Downloaded：0: IC training materials, including CMOS IC basic knowledge and the UNIX operating system. yes ppt format.
Date : 2025-05-16 Size : 2.59mb User : 刘有耀
timeconstraint Downloaded：0: VHDL programming timing constraints, there are two PDF documents, said very detailed, immediately download the
Date : 2025-05-16 Size : 308kb User : cenvi
FSKmodemodulateVHDLprogramme Downloaded：0: FSK modulation and demodulation of VHDL source code and simulation of the guide is the word document open.
Date : 2025-05-16 Size : 51kb User : 吴涛
FPGAdesignstudy Downloaded：0: introduced FPGA design the whole process and some simple examples
Date : 2025-05-16 Size : 213kb User : 谭建军

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