VHDL-FPGA-Verilog List Page 4194

VHDL-FPGA-Verilog list

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cordic_vhdl2 Downloaded：0: use cordic achieve trigonometry calculations, using achieve vhdl
Date : 2025-05-18 Size : 3kb User : 张力
my_ramlib_06 Downloaded：0: including various types of memory VHDL description, such as FIFO, Dual Port RAM, etc.
Date : 2025-05-18 Size : 601kb User : ruan
count60_dec_bcd_led Downloaded：0: is done in the laboratory in the loss of 60 counts, and LED show.
Date : 2025-05-18 Size : 313kb User : qqq
ata_6_DMAIPCORE.tar Downloaded：0: the latest ATA-6 bus protocol source code reference, achieving DMA, PIO Mode, can be linked to CDROM, IDE hard drive, CF card.
Date : 2025-05-18 Size : 817kb User : 喻袁洲
SDmmcfpgaconfig.tar Downloaded：0: MMC card VHDL source code to achieve, through large-scale production test
Date : 2025-05-18 Size : 5kb User : 喻袁洲
ps2_soc2 Downloaded：0: PS2 source VHDL, and can be connected directly to the computer. So the mouse, keyboard interface.
Date : 2025-05-18 Size : 21kb User : 喻袁洲
simple_fm_receiver.tar Downloaded：0: FM radio decoder and controller VHDL, Xilinx provide. I thank other.
Date : 2025-05-18 Size : 69kb User : 喻袁洲
arith_lib_cadence Downloaded：0: Cadence VHDL Operational the package, seeking to achieve root, You are not square did not know how get. Ha ha.
Date : 2025-05-18 Size : 80kb User : 喻袁洲
arith_lib_standard Downloaded：0: This is the standard for the whole ah, not 1164.vhd are some increases, multiplication, addition, operational square packages to come.
Date : 2025-05-18 Size : 80kb User : 喻袁洲
pinliji Downloaded：0: all passed, I was carefully designed, fully meet the requirements of beginners.
Date : 2025-05-18 Size : 1kb User : 李伟
shopdesigned Downloaded：0: all passed, I was carefully designed, fully meet the requirements of beginners.
Date : 2025-05-18 Size : 2kb User : 李伟
counter99 Downloaded：0: all passed, I was carefully designed, fully meet the requirements of beginners. 0-99 automatic counting
Date : 2025-05-18 Size : 1kb User : 李伟

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