VHDL-FPGA-Verilog List Page 4189

VHDL-FPGA-Verilog list

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calcu_synthesis Downloaded：0: the program two integers and the sum of squared output
Date : 2025-05-18 Size : 3kb User : 李铭
prssdoc Downloaded：0: VHDL code based on the cultural code useful but may be under the wrong heart is dumping
Date : 2025-05-18 Size : 2kb User : 轩辕李
sixuanyi Downloaded：0: four elected a selector, the importation of four, Output 1. When NM = 00 A at the election when NM = 01 am when the election NM B = C 10:00 when the election NM = 11:00 election D
Date : 2025-05-18 Size : 13kb User : 赵总令
yiwei Downloaded：0: Bomadeng-shift register is a six lights, without delay entity
Date : 2025-05-18 Size : 1kb User : 123
data_transfer Downloaded：0: synchronous serial data transmission circuit SSDT the basic function is to convert parallel data into serial and the same this step. System write and read sequential fully compatible Intel8086 timing. Synchronized signal
Date : 2025-05-18 Size : 544kb User : chengp
PCM30 Downloaded：0: SHIFT_8REG is eight with a displacement of the functional Register, Each will enter the data from the register into the lowest point, and the left shift accordingly. ODD_110BREG is a three backup Register, the Register i
Date : 2025-05-18 Size : 836kb User : chengp
TOKEN_vrilog Downloaded：0: synchronous serial data transmission circuit SSDT the basic function is to convert parallel data into serial and the same this step. System write and read sequential fully compatible Intel8086 timing. Synchronized signal
Date : 2025-05-18 Size : 355kb User : chengp
jurbojtag Downloaded：0: turbo jtag CPLD source code use altera EPM7 128S
Date : 2025-05-18 Size : 2kb User : z8848
key_prog Downloaded：0: easy-to-read 4* 4 keyboard and display program. To the preparation of other forms of keyboard scan procedures are certain guiding significance.
Date : 2025-05-18 Size : 140kb User : xht
usb11_systemc Downloaded：0: USB 1.1 PHY code systemc language USB 1.1 PHY code, systemc languages, including systemc based testbench language, doc and related documents
Date : 2025-05-18 Size : 189kb User : 里晓军
EDA_jiaotongdeng Downloaded：0: "digital circuit EDA portal-VHDL program examples"-- traffic lights procedures example
Date : 2025-05-18 Size : 3kb User : 张文
qicheweidengkongzhi Downloaded：1: car taillight control system controller car taillight VHDL program
Date : 2025-05-18 Size : 2kb User : 张文

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