VHDL-FPGA-Verilog List Page 4125

VHDL-FPGA-Verilog list

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opb_ac97_v2_00_a Downloaded：0: FPGA-based soft and LM4550B the AC97 sound card driver VHDL language, version 2.0
Date : 2025-05-20 Size : 65kb User : 张力
opb_ps2_dual_ref_v1_00_a Downloaded：0: Based on Xilinx FPGA realize PS2 keyboard and mouse interface. Version 1.0
Date : 2025-05-20 Size : 16kb User : 张力
SDR_4Mx16_HY57V641620HG_verilogl Downloaded：0: Hynix company 8M byte sdr sdram realize the Verilog simulation language.
Date : 2025-05-20 Size : 103kb User : 张力
PS2_LCD Downloaded：0: 1, ps/2 keyboard input, through the led display ascii code 2, wait 1s in the lcd display characters input 3, which backspce keys on the keyboard was required to settle the screen 4, when the lcd display full of character
Date : 2025-05-20 Size : 589kb User : bayernb
pinlv Downloaded：0: Based on SCM and CPLD
Date : 2025-05-20 Size : 264kb User : 王攀
s_fifo Downloaded：0: Verilog language describes a synchronous fifo, including: Fifo using declared registers for storage and Fifo using (model of) standard memory chip for storage. In two ways, including Testbench
Date : 2025-05-20 Size : 2kb User : 彭帅
adc0809 Downloaded：0: VHDL prepared ADC0809 controller, no errors verified
Date : 2025-05-20 Size : 1kb User : 王攀
CompilerOptimizations Downloaded：0: To increase simulation speed, ModelSim® can apply a variety of optimizations to your design. These include, but are not limited to, mergingprocesses, pulling constants out of loops, clock suppression, and signal colla
Date : 2025-05-20 Size : 51kb User : zhangyg
keyboad Downloaded：0: VHDL 4* 4 keyboard code
Date : 2025-05-20 Size : 1kb User : 王攀
ram Downloaded：0: RAM prepared VHDL example
Date : 2025-05-20 Size : 2kb User : 王攀
Vhdl_Simulation_With_Modelsim Downloaded：0: Triscend supports the use of the Model Technology ModelSim logic simulator for VHDL simulation of designs implemented in the Configurable System Logic (CSL) portion of a Triscend device.
Date : 2025-05-20 Size : 51kb User : zhangyg
generic_avalon_sram Downloaded：0: A comparison reference value has sram IP core, on the SOPC interested people have a certain guide! The procedure is used avalon bus, can be directly embedded into the SOPC Builder.
Date : 2025-05-20 Size : 5kb User : 林盈

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