VHDL-FPGA-Verilog List Page 4121

VHDL-FPGA-Verilog list

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S6_VGA_change Downloaded：0: Verilog source code, quartusII works. Procedures to achieve VGA timing. VGA graphics display control output. QuartusII in the direct run-off,
Date : 2025-08-16 Size : 2.45mb User : 李晨
lcd Downloaded：0: Use FPGA to control the program of 2* 16LCD, use VHDL language to write, and I convert him to verilog language, interested please contact;
Date : 2025-08-16 Size : 1kb User : 赵雯
Electronwatch Downloaded：0: This a vhdl programme for realise an electron watch by max-plus II. The function includes time showing and time setting. It may be extended to other functions like alarming clock and so forth.
Date : 2025-08-16 Size : 1kb User : 施红希
SystemOfTaxiFeeBasedOnVerilogHDL Downloaded：0: Abstract: Shanghai taxi meter as an example, the use of Verilog HDL language designed taxi meter so that it will have the time display, billing, as well as analog taxis to start, stop, reset and other functions, and set
Date : 2025-08-16 Size : 207kb User : 杨轶帆
oneperiod Downloaded：0: Will be sinusoidal segmentation, digital processing, that is, dds technology, ready to do for the Verilog
Date : 2025-08-16 Size : 3kb User : 严新文
fifo Downloaded：0: The use of Verilog language, the FPGA configuration into a fifo
Date : 2025-08-16 Size : 19kb User : achesser
smj_etester Downloaded：0: Pulse width Tester FPGA chip VHDL core procedures
Date : 2025-08-16 Size : 1kb User : 孙明杰
uart_verilog Downloaded：0: Simplified serial communication, removing the parity bit, the baud rate to 9600, test, fpga model xinlinx vp20
Date : 2025-08-16 Size : 5kb User : 刘红亮
ADC0809 Downloaded：0: VerlogHDL code, displaying the decoding of data read by AD0809, and the way to find a table
Date : 2025-08-16 Size : 1kb User : 刘红亮
AD9851 Downloaded：0: Using VHDL language DDS sine function generator
Date : 2025-08-16 Size : 489kb User : cfsword
vhdlexample Downloaded：0: Detailed features: when the company had to learn VHDL Engineer to the old classic examples, learn from each other.
Date : 2025-08-16 Size : 24kb User : 万葵
div3 Downloaded：0: VHDL to achieve 50 duty cycle. And is odd-numbered sub-frequency.
Date : 2025-08-16 Size : 115kb User : skylinnan

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