VHDL-FPGA-Verilog List Page 4081

VHDL-FPGA-Verilog list

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ram_read_write Downloaded：0: This procedure is for the FPGA system design a simple data storage and reading of small procedures, MAXPLUS2 prepared
Date : 2025-05-23 Size : 184kb User :
chuankou_data_send Downloaded：0: This is the FPGA system with a simple PC serial communication of small programs, MAXPLUS2 prepared
Date : 2025-05-23 Size : 98kb User :
testled Downloaded：0: For the FPGA system designed to control a simple LED lights to display a small program to prepare MAXPLUS2
Date : 2025-05-23 Size : 67kb User :
DE2_Synthesizer Downloaded：1: Use this source code can use the ALTERA DE2 development board will be turned into an electric piano keyboard
Date : 2025-05-23 Size : 107kb User : 林哲
DE2_Web_Server Downloaded：0: ALTERA DE2 development board DM9000A a network chip and the application example of a web page embedded into the DE2 development board in
Date : 2025-05-23 Size : 2.62mb User : 林哲
code Downloaded：0: Verilog language to write a simple eight processors. There are eight modules, addition operations can be carried out.
Date : 2025-05-23 Size : 7kb User : jay
Microsoft Downloaded：0: VHDL-based design of the divider, which is a useful source for all of us hope.
Date : 2025-05-23 Size : 3kb User : sun
vhd Downloaded：0: err
Date : 2025-05-23 Size : 122kb User :
multi_frequent Downloaded：0: Detailed octave, IBUFG, BUF, hope you like
Date : 2025-05-23 Size : 441kb User : 周辉
uart(serial)-200792511240998 Downloaded：0: VHDL-based serial interface with a complete process
Date : 2025-05-23 Size : 259kb User : weixing
coverlater Downloaded：0: This procedure is in circumstances Quartus7.2 compile a simple (2,1,3) convolutional code, can successfully compile and simulation.
Date : 2025-05-23 Size : 1kb User : 柯陡
Output_Decoded_FSMs Downloaded：0: Finite state machine of the parallel encoding, parallel coding can effectively improve the system the highest frequency, sub-state time to fully be used.
Date : 2025-05-23 Size : 6kb User : letter

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