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VHDL-FPGA-Verilog list
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Test_Bench
Downloaded:0
Eight test vectors (Test_Bench) and example of waveform generator (VHDL language, development environment: FPGA)
Date
: 2025-05-23
Size
: 12kb
User
:
11
jishu
Downloaded:0
Counter inside the FPGA and procedures related to information aggregation Guinness
Date
: 2025-05-23
Size
: 87kb
User
:
11
i2c
Downloaded:0
Based on the VHDL language to achieve the I2C-bus design, can be actually used
Date
: 2025-05-23
Size
: 193kb
User
:
赵杰
div3
Downloaded:0
Using VHDL hardware description language to achieve a good run of one-third frequency circuit
Date
: 2025-05-23
Size
: 1kb
User
:
赵杰
io_lvds
Downloaded:0
Based on the VHDL language, Low Voltage Differential Interface Specification realization
Date
: 2025-05-23
Size
: 130kb
User
:
赵杰
miaobiao
Downloaded:0
Complete countdown stopwatch design (with flashing instructions) VHDL code, Quartus 2 development environment, Archive documents, in Quartus2 can extract.
Date
: 2025-05-23
Size
: 111kb
User
:
李淡
simple_MCU
Downloaded:0
CPU design methods and processes! VERILOG hdl
Date
: 2025-05-23
Size
: 204kb
User
:
正中
verilog9999
Downloaded:0
Verilog achieve the 9999 count, which took part in the frequency module, counting module, decoding, dynamic display scanning with digital display,
Date
: 2025-05-23
Size
: 306kb
User
:
ouyang
2x8bit_dac
Downloaded:0
With EPM7032 (CPLD) to do 2-way 8-bit parallel input DAC, with the internal ring oscillator (no external clock oscillation source).
Date
: 2025-05-23
Size
: 3kb
User
:
邵刚
quartus6.0
Downloaded:0
Atlera company quartus 6.0 to develop the software platform of the license
Date
: 2025-05-23
Size
: 2kb
User
:
guobo
yibutongxin
Downloaded:0
err
Date
: 2025-05-23
Size
: 545kb
User
:
王权
uart
Downloaded:0
Using Verilog realization of serial asynchronous communication, applied to RS232
Date
: 2025-05-23
Size
: 1.07mb
User
:
王权
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.73
.74
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.76
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4078
.79
.80
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.82
.83
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4310
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