VHDL-FPGA-Verilog List Page 4018

VHDL-FPGA-Verilog list

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DDR2_module_VHDL_test(Rev0.1) Downloaded：0: ddr 2 interface test module ddr 2 read and write interface to read and write test module
Date : 2025-05-25 Size : 123kb User : 骑士
vhdl-core-Kopie_von_mem32_vhd Downloaded：0: VHDL module nand flash control, the FPGA to realize the direct read and write control NAND FLASH.
Date : 2025-05-25 Size : 4kb User : 骑士
memio Downloaded：0: Latest VHDL modules to realize the control of SRAM can be directly used for ALTEAR XILLIX such as FPGA, the
Date : 2025-05-25 Size : 7kb User : 骑士
newlin-pwm Downloaded：0: VHDL source module can realize the most classic original PWM, which can be used for power supply and motor control
Date : 2025-05-25 Size : 1kb User : 骑士
kuaijintuiyinyueshizhong_VHDL Downloaded：0: The program is to simulate the clock program of the school; CLK - clock signal, RST - zero signal, set_en- school To signal, faster-- fast forward signal, slower-- quick exit signal, hour-- hour school, min-- minute scho
Date : 2025-05-25 Size : 110kb User : wang
dianziqin_VHDL Downloaded：0: Autoplay octave flower design, contains detailed procedures, notes, schematics, etc.
Date : 2025-05-25 Size : 78kb User : wang
LEDhanzigundong_VHDL Downloaded：0: This paper mainly discusses the use of EDA tools for the design of Chinese characters scrolling display technology. First, the description based on field programmable gate array (FPGA) hardware circuit and then studied i
Date : 2025-05-25 Size : 181kb User : wang
mimasuo_VHDL Downloaded：0: The function and characteristics of V HDL language are briefly described Eight serial digital lock design as an example, introduced in Max + plus Ⅱ 10. 2 develop software, set with V HDL hardware description language The
Date : 2025-05-25 Size : 348kb User : wang
zhuangtaijijtd_VHDL Downloaded：0: The methods of VHDL and finite state machine are designed to control the traffic signals of the main road and trunk road System. Define the different status of the lights in the traffic light at the intersection. The jun
Date : 2025-05-25 Size : 137kb User : wang
s3esk_startup Downloaded：0: This is a VHDL language used to write drivers for the LCD! Hope useful for everyone
Date : 2025-05-25 Size : 3kb User : 钟跃民
VHDL_TIMERCHIP_Design Downloaded：0: VHDL-based timing count chip design through modular, state diagram design timing chip
Date : 2025-05-25 Size : 196kb User : 郭鑫俊
simulink-03-31 Downloaded：0: Based on MATLAB/DSP Build controllable signal generator, by the Matlab modeling synthesis, and generates VHDL code, adopted by the Quartus compiler.
Date : 2025-05-25 Size : 291kb User : ltianyang

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