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4 switch used as a motor control signal, respectively, as follows: left, right, brake failure and
Date : 2025-05-26 Size : 1kb User : 赵国良

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16-bit fixed-point FFT-DSP realize the FPGA, the relevant code and practical description
Date : 2025-05-26 Size : 3.66mb User : 杨合

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The Verilog language describes Intel8255 IP Core. I have already passed physical verification in a project, which can be directly used in FPGA synthesis or ASIC synthesis.
Date : 2025-05-26 Size : 6kb User : David.Mr.Liu

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UART16550 compatible serial communication controller, Verilog language description, the use of Altera Cyclone series FPGA chip integrated, as part of the use of FIFO to the internal resources to achieve. Projects have be
Date : 2025-05-26 Size : 10kb User : David.Mr.Liu

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100 cases of classic VHDL Tutorial contains 100 commonly used hardware source code
Date : 2025-05-26 Size : 237kb User : bestyuan111

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Adc 0809 digital mode conversion chip fpga control program
Date : 2025-05-26 Size : 56kb User : conanhfl

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17FIR 瞬 VHDL 爰?说 牡 苑
Date : 2025-05-26 Size : 1005kb User : fangyingjie

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Water lamp, used in lieu of Seven-Segment LED digital tube lights, water interval 1 seconds, digital tube displays
Date : 2025-05-26 Size : 244kb User : 王传辉

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For the KEIL C language keyboard scanning program, some of them are not correct to be modified
Date : 2025-05-26 Size : 1kb User :

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Frequency divider is one of the basic units in FPGA design. Although at present in most also widely used in the design of integrated phase locked loop (DLL) such as altera PLL, Xilinx for clock frequency division, double
Date : 2025-05-26 Size : 2kb User : 王子

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In the EDA
Date : 2025-05-26 Size : 55kb User : 林超勇

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In MAX+ PLUS II environment prepared using VHDL Adder
Date : 2025-05-26 Size : 34kb User : 林超勇
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