VHDL-FPGA-Verilog List Page 4011

VHDL-FPGA-Verilog list

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fifo8_8 Downloaded：0: 8* 8 of the fifo data buffer of the VHDL source code. After quartus ii 6.0 proved to be successful.
Date : 2025-05-26 Size : 1kb User : 李松
clock_design Downloaded：0: Digital Clock in Verilog code, quartusII development environment.
Date : 2025-05-26 Size : 405kb User : 屈开
16bitadder Downloaded：0: The 16-bit fast adder verilong is well worth seeing
Date : 2025-05-26 Size : 3kb User : 屈开
DDSverilogsource Downloaded：0: DDS of the Verilog source code, please support the U.S. more than
Date : 2025-05-26 Size : 3kb User : 屈开
DM9000A_IPcose Downloaded：0: Such as the title: dm9000aIP nuclear, after verification, can be used
Date : 2025-05-26 Size : 17kb User : yt
sine Downloaded：0: Verilog programming, the use of FPGA realize two sinusoidal output signals can also be extended into a six-way sinusoidal output
Date : 2025-05-26 Size : 4.57mb User : 陈剑
DDS-320-modu Downloaded：0: 320x240 screen using the design of experiments to run me generate sine wave, AM FM waveforms, sweep.
Date : 2025-05-26 Size : 1.19mb User : hangyinli
PWM Downloaded：0: FPGA using VHDL language realize the PWM output waveform, duty cycle controlled
Date : 2025-05-26 Size : 36kb User : 王传辉
watchgai Downloaded：0: Use of FPGA development board of the V4 produced electronic watches, the use of VHDL language
Date : 2025-05-26 Size : 1.06mb User : 王传辉
8255_IO_vhdl Downloaded：0: VHDL Language Design 8255 Parallel I/O interface chip
Date : 2025-05-26 Size : 1kb User : weixj
adc0809 Downloaded：0: ADC0809 driver, after the experiment to accurate and reliable, practical
Date : 2025-05-26 Size : 1kb User : chenyang
UART Downloaded：1: Input clock 20M, the baud rate for 9600, Serial transceiver functions, by modifying the frequency of some other baud rate coefficient can realize the transceiver
Date : 2025-05-26 Size : 7kb User : 杨启勇

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