I2C(VHDLVerilogHDL) Have two, one with VHDL prepar

I2C(VHDLVerilogHDL)

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Category : VHDL-FPGA-Verilog
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Update : 2012-11-26
Size : 502kb
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Author ：sun****
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Have two, one with VHDL prepared I2C, a Verilog hdl languages

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Filename	Size	Update
I2C总线VHDL	Verilog HDL源码
...........................\i2c
...........................\...\i2c
...........................\...\...\bench
...........................\...\...\.....\CVS
...........................\...\...\.....\...\Entries
...........................\...\...\.....\...\Repository
...........................\...\...\.....\...\Root
...........................\...\...\.....\verilog
...........................\...\...\.....\.......\CVS
...........................\...\...\.....\.......\...\Entries
...........................\...\...\.....\.......\...\Repository
...........................\...\...\.....\.......\...\Root
...........................\...\...\.....\.......\i2c_slave_model.v
...........................\...\...\.....\.......\spi_slave_model.v
...........................\...\...\.....\.......\tst_bench_top.v
...........................\...\...\.....\.......\wb_master_model.v
...........................\...\...\CVS
...........................\...\...\...\Entries
...........................\...\...\...\Repository
...........................\...\...\...\Root
...........................\...\...\doc
...........................\...\...\...\CVS
...........................\...\...\...\...\Entries
...........................\...\...\...\...\Repository
...........................\...\...\...\...\Root
...........................\...\...\...\i2c_specs.pdf
...........................\...\...\...\src
...........................\...\...\...\...\CVS
...........................\...\...\...\...\...\Entries
...........................\...\...\...\...\...\Repository
...........................\...\...\...\...\...\Root
...........................\...\...\...\...\I2C_specs.doc
...........................\...\...\documentation
...........................\...\...\.............\CVS
...........................\...\...\.............\...\Entries
...........................\...\...\.............\...\Repository
...........................\...\...\.............\...\Root
...........................\...\...\rtl
...........................\...\...\...\CVS
...........................\...\...\...\...\Entries
...........................\...\...\...\...\Repository
...........................\...\...\...\...\Root
...........................\...\...\...\verilog
...........................\...\...\...\.......\CVS
...........................\...\...\...\.......\...\Entries
...........................\...\...\...\.......\...\Repository
...........................\...\...\...\.......\...\Root
...........................\...\...\...\.......\i2c_master_bit_ctrl.v
...........................\...\...\...\.......\i2c_master_byte_ctrl.v
...........................\...\...\...\.......\i2c_master_defines.v
...........................\...\...\...\.......\i2c_master_top.v
...........................\...\...\...\.......\timescale.v
...........................\...\...\...\vhdl
...........................\...\...\...\....\CVS
...........................\...\...\...\....\...\Entries
...........................\...\...\...\....\...\Repository
...........................\...\...\...\....\...\Root
...........................\...\...\...\....\I2C.VHD
...........................\...\...\...\....\i2c_master_bit_ctrl.vhd
...........................\...\...\...\....\i2c_master_byte_ctrl.vhd
...........................\...\...\...\....\i2c_master_top.vhd
...........................\...\...\...\....\readme
...........................\...\...\...\....\tst_ds1621.vhd
...........................\...\...\sim
...........................\...\...\...\CVS
...........................\...\...\...\...\Entries
...........................\...\...\...\...\Repository
...........................\...\...\...\...\Root
...........................\...\...\...\i2c_verilog
...........................\...\...\...\...........\CVS
...........................\...\...\...\...........\...\Entries
...........................\...\...\...\...........\...\Repository
...........................\...\...\...\...........\...\Root
...........................\...\...\...\...........\run
....................

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