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VHDL-FPGA-Verilog list
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Nios nuclear entry of the tutorial to use the simplest, one school will be, painless entry.
Date : 2025-05-26 Size : 903kb User : 梁奔山

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CPLD/FPGA module with commonly used integrated system design example CD-ROM program
Date : 2025-05-26 Size : 16.65mb User :

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The use of DDS technology waveform generator, FPGA realization.
Date : 2025-05-26 Size : 499kb User :

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VHDL language with my own series of 16-order FIR digital filter in the Quartus II simulation is adopted, the U.S. will certainly be helpful, compressed document also detailed design description, it certainly allows you t
Date : 2025-05-26 Size : 888kb User : 王志

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General FIFO's VHDL programming word depth and word length can be designed by itself
Date : 2025-05-26 Size : 1kb User : danny

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Video controller FPGA design, FED-driven control system design and FPGA
Date : 2025-05-26 Size : 1.94mb User : 雅兰

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Parallel to serial VHDL description: Based on the FPGA to send the SPI module
Date : 2025-05-26 Size : 93kb User : yaoqinghua

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altera of timing constraints files, helpful
Date : 2025-05-26 Size : 1.32mb User : back1202

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Under NIOS, the image is displayed on the LCD screen, and the full hardware implementation based on the DE2 board is now used to burn the image to SDRAM, which can then be displayed directly to the LCD screen.
Date : 2025-05-26 Size : 1.18mb User : 刘赛

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VHDL design of the measurement procedures DS18B20 welcome Please do not directly copy the test may not show.
Date : 2025-05-26 Size : 7kb User : aaaa

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VHDL control ADC0809 chip realize after AD conversion and acquisition of reading and writing data.
Date : 2025-05-26 Size : 4kb User : zhou129

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Abstract: the digital combination lock mainly complete the lock, password, the password verification, open electric lock, password changes, etc. The design of the digital combination lock circuit mainly includes 11 modul
Date : 2025-05-26 Size : 696kb User : 孙光华
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